Low power design

Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate design we cannot implement any technique that is gate specific, it has to be a global technique.
  1. Multi-Vdd, variable Vdd and Multi-Vth seems to be a good global solution.
  2. Reducing the clock speed will result in low power consumption, but on the cost of performance.
  3. Using power headers and power footer transistors on logic gates cuts down power.
  4. You could separate the design in blocks, which can go in to sleep mode.
  5. Another solutions is variable VDD and variable frequency (as Intel or AMD do).This means, you adapt VDD and frequency to the necessary performance.
  6. Gated clocks and Logic Addressable clocks, dis adv - timing problems due to improper latching of signals, and difficult to test.
  7. -ve edge triggered flops, (nor+inv) = 1.5 gates, +ve edge triggered flops, (and+inv) = 2.5 gates, so -ve has less gates, less glitching and hence low power.

Any more thoughts and ideas are welcome.