Modeling Guideline: Do not place delays on the LHS/RHS of blocking assignments to model combinational logic.
Modeling Guideline: Do not place delays on the LHS of nonblocking assignments to model combinational logic.
assignments for either modeling or testbench generation is discouraged.
Modeling Guideline: Place delays on the RHS of nonblocking assignments only when trying to model transport output-propagation behavior. This coding style will accurately model delay lines and combinational logic with pure transport delays; however, this coding style generally causes slower simulations.
assignment of subsequent stimulus events in the same procedural block.
Modeling Guideline: In general, do not place delays on the RHS of nonblocking assignments to model combinational logic. This coding style can be confusing and is not very simulation efficient. It is a common and sometimes useful practice to place delays on the RHS of nonblocking assignments to model clock-to-output behavior on sequential logic.
Modeling Guideline: Use continuous assignments with delays to model simple combinational logic. This coding style will accurately model combinational logic with inertial delays.Use always blocks with no delays to model complex combinational logic that are more easily rendered using Verilog behavioral constructs such as "case-casez-casex", "if-else", etc. The outputs from the no-delay always blocks can be driven into continuous assignments to apply behavioral delays to the models. This coding style will accurately model complex combinational logic with inertial delays.
Any delay added to statements inside of an block does not accurately model the behavior hardware and should not be done. The one exception carefully add delays to the right hand side of nonblocking assignments, which will accurately model transport delays, generally at the cost of simulator performance.
Adding delays to any sequence of continuous assignments, or modeling complex logic with no inside of an always block and driving the always outputs through continuous assignments with delays, accurately model inertial delays and are recommended coding styles for modeling combinational logic.