Interview Question - Testing


As time goes by, the average number of transistors on a chip is increasing faster than the number of input/output pins. Assuming this trend continues, describe the affect it will likely have on how circuits are tested.

Interview Question


If we increase the supply voltage for a circuit, answer whether the short-circuiting current is most likely to increase, stay the same, or decrease. If you don't have enough information to predict the effect on the short-circuiting current, describe what information you need, how you would obtain the information, and how you would use the information to predict the effect of an increase in the supply voltage on the short circuiting current.

Interview Question


Some software programming languages allow compilers to perform "short cut" or "short circuit" optimizations on AND and OR operations. In a short-cut AND or OR, the second argument is not evaluated if the first argument evaluates to a controlling value. For example, in evaluating f(x) AND g(y), if f(x) is false, then g(y) will not be evaluted.
  1. Answer whether this optimization is feasible and beneficial in hardware.

Interview Question


Due to a miscommunication during design, you thought your circuit was supposed to have a supply voltage of 2.1 volts (threshold voltage is 0.7 volts) and a 25 ns cycle time, and you designed it to meet those specifications. Now your boss tells you you were supposed to have a 20 ns cycle time. To avoid redesigning the whole circuit, a co-worker suggests increasing the voltage of the circuit to decrease the delay to 20 ns. The same co-worker suggests picking some arbitrary number like 3.5 volts.
  1. Determine the new cycle time of your circuit with a 3.5 volt input voltage.
  2. Your boss is worried about the additional power consumption - calculate the increase in power consumption of your circuit at 3.5 volts, assuming activity factor and capacitance remain the same and neglecting short circuit and leakage power.
  3. To satisfy your boss, calculate the minimum voltage you would increase the supply voltage to, in order to allow your circuit to run at 20 ns. You may leave your answer in non-simplified numeric terms, but not in the form of an equation to solve.

Interview Question


Your group designs a microprocessor for use in cell phones and palmtop computers. You currently fabricate your chips on a 0.13micron process. A new fabrication facility with a 90nm process has asked you if you would like to switch to their facility.

What do you believe will be the three most important tradeoffs between remaining with the 0.13 micron fabrication process and switching to the 90nm process?

Interview Question


The average performance of products in your market segment triples every 36 months. Your design engineers have proposed an optimization that will increase performance by 12%. The optimization will postpone the completion date of the project by 2 months. Should the engineers implement the optimization and postpone the completion date, or should they stick to the original schedule?

Interview Question


When trying to validate the behavior of a circuit under boundary conditions, would you use coverage monitors or assertions? Why?

Interview Question


When writing a specification for a circuit, the specification should be "obviously correct". What does this mean? Illustrate with an example.

Interview Question


What are the main differences between reference model testbenches and relational style testbenches? For what types of circuits would each be used and why?

Interview Question


For a system with 64 primary inputs, 1024 internal states, 6,120 combinational signals, and 14 primary outputs, how many test cases need to be considered in order to fully exercise the system?

Interview Question


Your task is to predict the maximum performance that you can achieve if you implement the following pseudocode in hardware with a single-port memory array in Question a and with a dual-port memory array in Question b.

for i := 0 to 254
{
if A[i] > A[i+1] then
{
tmp := A[i+1];
A[i+1] := A[i];
A[i] := tmp;
}
}

Question a: If you use a single-port memory array, what is the minimum number of clock cycles that your circuit will need to perform the above loop?

Question b: If you use a dual-port memory with one read port and one read/write port, what is the minimum number of clock cycles that your circuit will need to perform the above loop?

Interview Question


The well-dressed marketing group just learned that a circuit you designed has undetectable faults. They are debating the consequences of having undetectable faults in a circuit.

The marketing people who wear Armani claim: Because an undetectable fault cannot be detected, it means that there might be something wrong in the circuit that won't be caught until the customer uses the circuit. Therefore the fault is a risk and your circuit should be changed to remove the fault.

The marketing people who wear Gucci claim: Because an undetectable fault cannot be detected, it cannot affect the behaviour of the circuit. Therefore the fault is harmless and your circuit should not be changed.

For each group (Armani and Gucci), explain what parts of their claim are correct and what parts are wrong.

Solutions to Interview Questions


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Interview Question - Low power


You are on a team that is exploring power reduction techniques for a new design. The details of the design and implementation are as follows:
  • The implementation technology has a nominal supply voltage of 1.8V and a threshold voltage of 0.4V.
  • At the nominal supply voltage, the design works at 500MHz.
  • The environment has two modes: high-bandwidth and low-bandwidth.
    • In the high-bandwidth mode, every clock cycle has valid data.
    • In the low-bandwidth mode, valid data arrives once every ten clock cycles (e.g. one clock cycle with valid data followed by ten cycles with invalid data.)
  • On average, the environment is in the high-bandwidth mode for 6 consecutive seconds and in the low bandwidth mode for 4 consecutive seconds.
  • The latency through the circuit is 3 cycles.
  • Short-circuit and leakage power are negligible.
One proposal for power reduction is to scale down the supply voltage when the circuit is in the low bandwidth mode.
Calculate how much saving can be achieved using the voltage scaling technique as a percentage of the original power consumption of the circuit.
NOTES:
  1. The scaled supply voltage is 1.2V.
  2. Supply scaling is done using a DC-DC converter whose power efficiency is 90% (i.e for every 100mW consumed in the converter, only 90mW are actually delivered to the circuit)
  3. The converter is inactive when the circuit operates at the nominal supply mode.
An alternative to voltage scaling is to use a clock gating scheme to turn the clock off when it is not needed.
Calculate the percentage of power that can be saved using this scheme.
NOTES:
  1. Clock gating circuit's area is 10% of the main circuit.
  2. The clock gating circuit has the same activity factor as the main circuit.
Which of the two techniques achieves a larger savings in power and how much more is it?
Your manager is proposing combining the two techniques in order to achieve additional power saving. Briefly discuss the possible limitations of this proposal.

Dataflow Diagrams


Dataflow diagrams are data-dependency graphs where the computation is divided into clock cycles.
  • Purpose:
    • Provide a disciplined approach for designing datapath-centric circuits.
    • Guide the design from algorithm, through high-level models, and finally to RTL code for the datapath and control circuitry.
    • Estimate area and performance.
    • Make tradeoffs between different design options.
  • Background
    • Based on techniques from high-level synthesis tools.
    • Some similarity between high-level synthesis and software compilation.
    • Each dataflow diagram corresponds to a basic block in software compiler terminology.
Dataflow Diagrams, Hardware, and Behavior:
To be completed..

Area Estimation:
  1. Maximum number of blocks in a clock cycle is the total number of that component that are needed.
  2. Maximum number of signals that cross a cycle boundary is the total number of registers that are needed.
  3. Maximum number of unconnected signal tails in a clock cycle is the total number of inputs that are needed.
  4. Maximum number of unconnected signal heads in a clock cycle is the total number of outputs that are needed.
Dataflow Diagram Execution:
To be completed..

Performance Estimation:
To be completed..

Design Analysis:
To be completed..

Area / Performance Tradeoffs:
To be completed..




Algorithms and High level models


For designs with significant control flow, algorithms can be described in software languages, flowcharts, abstract state machines, algorithmic state machines, etc.
For designs with trivial control flow (e.g. every parcel of input data undergoes the same computation), data-dependency graphs are a good way to describe the algorithm.
For designs with a small amount of control flow (e.g. a microprocessor, where a single decision is made based upon the opcode) a set of data-dependency graphs is often a good choice.
  1. When creating an algorithmic description of your hardware design, think about how you can represent parallelism in the algorithmic notation that you are using, and how you can exploit parallelism to improve the performance of your design.
  2. Flow charts and various flavors of state machines, everything that you might 've learned about these forms of description are also applicable in hardware design. In addition, you can exploit parallelism in state machine design to create communicating finite state machines. A single complex state machine can be factored into multiple simple state machines that operate in parallel and communicate with each other.
  3. In software, the expression: (((((a + b) + c) + d) + e) + f) takes the same amount of time to execute as: (a + b) + (c + d) + (e + f). But, remember: hardware runs in parallel. In algorithmic descriptions, parentheses can guide parallel vs serial execution.
  4. Data dependency graphs capture algorithms of datapath-centric designs.Datapath-centric designs have few, if any, control decisions: every parcel of input data undergroes the same computation.
There are many different types of high-level models, depending upon the purpose of the model and the characteristics of the design that the model describes. Some models may capture power
consumption, others performance, others data functionality. High-level models are used to estimate the most important design metrics very early in the design cycle. If power consumption is more important than performance, then you might write highlevel models that can predict the power consumption of different design choices, but which has no information about the number of clock cycles that a computation takes, or which predicts the latency inaccurately. Conversely, if performance is important, you might write clock-cycle accurate high-level models that do not contain any information about power consumption.

Conventionally, performance has been the primary design metric. Hence, high-level models that predict performance are more prevalent and more well understood than other types of high-level models. There are many research and entrepreneurial opportunities for people who can develop tools and/or languages for high-level models for estimating power, area, maximum clock speed, etc.

Interview question - Fabrication, Hypothesis, Power, Process


While you are eating lunch at your regular table in the company cafeteria, a vice president sits down and starts to talk about the difficulties with a new chip. The chip is a slight modification of existing design that has been ported to a new fabrication process. Earlier that day, the first sample chips came back from fabrication. The good news is that the chips appear to function correctly. The bad news is that they consume about 10% more power than had been predicted. The vice president explains that the extra power consumption is a very serious problem, because power is the most important design metric for this chip. The vice president asks you if you have any idea of what might cause the chips to consume more power than predicted
  1. Hypothesize a likely cause for the surprisingly large power consumption, and justify why your hypothesis is likely to be correct.
  2. Briefly describe how to determine if your hypothesized cause is the real cause of the surprisingly large power consumption.
  3. The vice president wants to get the chips out to market quickly and asks you if you have any ideas for reducing their power without changing the design or fabrication process. Describe your ideas, or explain why her suggestion is infeasible.

Interview question - Clock and Voltage


Increasing clock speed without increasing power...
The following are given:
  • You need to increase the clock speed of a chip by 10%
  • You must not increase its dynamic power consumption
  • The only design parameter you can change is supply voltage
  • Assume that short-circuiting current is negligible
How much do you need to decrease the supply voltage by to achieve this goal?

What problems will you encounter if you continue to decrease the supply voltage?


In each low power approach described below identify which components of a typical power equation are being minimized or maximized.
  1. Designers scaled down their ASIC.
  2. The Transistors were made larger.
  3. All inputs to functional units are registered.
  4. Gray coding of signals is used for address signals.

Interview question - Power & Area


One day you are strolling the hallways in search of inspiration, when you bump into a person from the marketing department.

The marketing department has been out surfing the web and has noticed that companies are advertising the MIPs/mm2, MIPs/Watt, and Watts/cm3 of their products. This wide variety of different metrics has confused them.

Explain whether each metric is a reasonable metric for customers to use when choosing a system. If the metric is reasonable, say whether "bigger is better" ( e.g. 500 MIPs/mm2 is better than 20 MIPs/mm2) or "smaller is better" (e.g. 20 MIPs/mm2 is better than 500 MIPs/mm2), and which one type of product (cell phone, desktop computer, or compute server) is the metric most relevant to.

Interview question


If you were to compare a typical digital circuit from 5 years ago with a typical digital circuit today, would you find that the percentage of the total clock period consumed by capacitive load has increased, stayed the same, or decreased?

Basic Timing - Interview question


Assume that the timing diagram shows the limits of the allowed times (either minimum or maximum). For each of the terms listed below, answer which time periods (one or more of t1 – t9 or NONE) are examples of the term.

















Clock Skew, Clock Period, Max Frequency.

Interview Questions


  1. If you have to write your own code (i.e. you do not have a library of memory components or a special component generation tool, what datastructures in VHDL would you use when creating a register file?
  2. When using VHDL for an FPGA, under what circumstances is it better to write your own VHDL code for memory, rather than instantiate memory components from a library?
  3. In this question there is a network that runs a protocol called BigLan. You are designing a router called the DataChopper that routs packets over the network running BigLan (i.e. they're BigLan packets). The BigLan network protocol runs at a data rate of 160 Mbps (Mega bits per second). Each BigLan packet contains 100 Bytes of routing information and 1000 Bytes of data.
    You are working on the DataChopper router, which has the following performance numbers:
    75MHz - clock speed
    500 number of clock cycles to process the routing information for a packet
    4 CPI for a byte of data
    • Which has a higher maximum throughput router, and how much faster is it?
    • Explain the effect of an increase in packet length on the performance of the DataChopper (as measured in the maximum number of bits per second that it can process) assuming the header
      remains constant at 100 bytes.
  4. If performance doubles every two years, by what percentage does performance go up every month? This question is similar to compound growth from your economics class.

No Answers will be provided.
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