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Of the handful of HVL choices available in the market SystemVerilog and e language (Specman) are the most popular and widely adopted by semiconductor companies. The reason for these two languages being the preferred choice is not just the language features itself but the accompanying methodology prescribed by the EDA vendors (ex: OVM/VMM for SV and eRM for e language). These methodologies provide guidelines to build modular, re-usable and extensible verification modules which support plug and play development. With most of the silicon designs today adopting the SoC (System-on-Chip) methodology where several design IPs are integrated on a single chip, there is a new requirement for corresponding verification IPs (VIP). By taking advantage of the VIPs available in market, the verification team can build a test environment for a complex SoC with minimal resource and time utilization. A standard verification methodology serves as a common platform for the various third party VIP developers and its customers. So it’s actually the verification methodology rather than the language which influences the decision on VIP selection. Some methodologies have made it possible to integrate verification modules written in different languages so that you don’t have to discard any legacy code if available (you may have to make it methodology compliant though). VIPs and verification methodologies are still relatively newer concepts to the verification world and is being tried out in experimental phases by semiconductor companies. Not all of the industry leaders have adopted these methodologies completely probably because of the overhead in training their current workforce and replacing the legacy code. Here’s hoping that the EDA vendors enhance their methodologies to make it more developer friendly.
A good verification plan addresses many questions like what tools can be used for stand alone and full chip and for what specific type of tests. Creation of expected result scenarios along with the self checking mechanism should be detailed to improve automation and to drive the highest return on performance. In addition to each verification phase, testbench deliverables, dependencies like RTL availability, milestones like tests to be completed or written and any assumptions need to be specified and understood thoroughly. Finally, upon completion of the verification plan it has to be reviewed by both the design and verification teams and a matrix has to be created to track test coverage and then use it to measure the completeness or progress. Is is also important to know when and how to apply technologies such as emulation and formal methods to leverage key strengths to avoid any weaknesses and achieve high design quality using the verfication effort.
Courtesy: Catherine Ahlshlager!
The working principles of the device are based on sequential tunneling of single electrons between the phosphorus atom and the source and drain leads of the transistor. The tunneling can be suppressed or allowed by controlling the voltage on a nearby metal electrode with a width of a few tens of nanometers.
Original research article has been published in Nano Letters on Dec. 1st, 2009:
Transport Spectroscopy of Single Phosphorus Donors in a Silicon Nanoscale Transistor,
Kuan Yen Tan, Kok Wai Chan, Mikko Möttönen, Andrea Morello, Changyi Yang, Jessica van Donkelaar, Andrew Alves, Juha-Matti Pirkkalainen, David N. Jamieson, Robert G. Clark, and Andrew S. Dzurak,
Nano Lett., Article ASAP, DOI: 10.1021/nl901635j (2009).
For more information, please contact:
Dr. Mikko Möttönen, Helsinki University of Technology, Department of Applied Physics, firstname.lastname@example.org, tel. +358 9 470 22342 or +358 50 594 0950
Prof. Andrew Dzurak, University of New South Wales, Centre for Quantum Computer Technology, a.dzurak [at] unsw.edu.au, tel. +61293856311
Defining clock jitter
Clock jitter and statistics
Technical skills are more profound in people with greater hands on experience. Needless to say, the more adventurous you are to dive deep and the more complex your targets are, the more you learn and this is where you really add value. Technical skills will eventually teach you how to meet these expectations.
Soft skills are the ones that define an engineer’s approach towards work and life and in most cases define stress that is more individual specific. Soft skills are actually people or inter-personnel skills. The best part about mastering it is that the application of these skills is not limited to one's profession, but their scope reaches beyond. Soft skills teach one to succeed, and to exceed expectations. There are situations that we come across during our day-to-day work life as a design or verification engineer in which one person performs better than the others just on the basis of Soft skills - be it winning an argument with someone on the basis of his/her communication or finding/handling multiple tasks effectively because of superior organizational abilities.
Soft skills are extremely important for engineers and this is something that is often overlooked. It is surprising that we spend most of our time educating almost exclusively in technical skills while thinking you are good at soft skills.
Our reactions in a complex setting vary widely with situations, emotions, requirements, time, belief, knowledge and expertise. Being such complex, a normal human being will be no exception at a work place where the stakes are very high. Therefore the quality of a job done by an engineer is directly proportional to his or her psychological maturity and profoundness acquired, adopted and developed with age and experience. be able to learn them.
VLSID 2010 features an exciting lineup of seventy technical papers, eight distinguished keynote speakers, and nine invited embedded tutorials/hot topic presentations on the three days of the conference (January 5 - 7). On the two days preceding the conference (January 3 - 4), there are eight tutorials, including one hands-on tutorial being organized for the first time in the history of the conference. Other events that will happen concurrently with the main conference include industry and education forums, exhibits, and Design/EDA/Systems contest.
The conference call for participation is available for viewing!!
You can now register online, and avail of early bird registration rates. If you need any further information, please feel free to write to organizing committee member Mohammed Hussain Mohammed.Hussain@synopsys.com
Regardless of whether or not they have the infrastructure to respond, here are some ways to look at it:
1. Is the feedback legitimate? There are many instances where the negativity actually has some merit. It's hard for everybody to have a pristine experience when issues pop up. In a lot of instances, the negative feedback is not about the overall work quality or efficiency, but is an exception to the rule. If the negative feedback is legitimate, it does require some kind of response. Does it require a personal response in every instance? Not necessarily. As long as the response is communicated in a human and personal way and mutually agreeable it could correct the course.
2. Is the person crazy? Don't laugh. It is possible. We've all read peer reviews and marvelled at how someone's review of a work package has no real attachment to the reality we all share. The world is full of crazy people who are just looking for a soapbox to be heard or a cause to take on. In this instance, you have to tread carefully. Responding may open up a can of worms that will see no end and no reason. No responding might only aggravate the individual. These are special/case-by-case instances, and they might require something more traditional - like a phone call - to try and resolve the scenario. If you get a mixed bag of Positive and Negative feedback very frequently from the same person, it just time to re-think your strategies.
3. Is apologizing an option? Apologies definitely go a long way. But be political and dont give away too much!
4. Should you just forget about it and move on? There are many schools of thoughts on this. Some people say you have to respond to each and every piece of feedback (both positive and negative), some argue that you should only respond to those who really do have some kind of impact, and then there is the group that simply sits backs and just lets it fly without ever responding. Your mileage may vary. Depending on the scenario, the type of feedback and the voices behind the noise, is how you will best gauge how to respond. It is usually good to respond in some kind of fashion so that your own POV (point of view) is - at least - a part of the conversation.
5. Should you respond to everything? It's very easy to respond to the good stuff, it is hard (and time consuming) to respond to the negative by citing justification and stuff. The answer to this one ties into #4. In a perfect world, yes - respond to everything (with the exception of the people in #2). In responding, you're not just answering to this one individual's gripe, you're better able to reflect on how your brand "lives" in people's minds, and I believe this will make you a better Marketer, a better Communications Professional and a better brand.
The problem is : there is no one who provides opensource EDA solutions for the real life. Although it is one problem, it is very complex in itself. In real life, designers use EDA software to design chips or circuit boards. Thereby the designer requires a set of hardware design tools to design his/her chips. However the same set of hardware design tools does not apply for every hardware design project.
FEL is the vision child of Chitlesh Goorah [Interview @ http://fedoraproject.org/wiki/Interviews/FEL)]...
* Fedora's EDA portfolio,
* an opensource EDA provider and
* opensource EDA community builder.
* Deployable in both development and production environments.
* No kernel patches are required, making it easy to deploy and use.
* No licenses required and it is free.
"Fedora Electronic Lab" targets mainly the Micro-Nano Electronic Engineering field. It introduces:
* a collection of Perl modules to extend Verilog and VHDL support.
* tools for Application-Specific Integrated Circuit (ASIC) Design Flow process.
* extra standard cell libraries supporting a feature size of 0.13µm. (more than 300 MB)
* extracted spice decks which can be simulated with gnucap/ngspice or any spice simulators.
* interoperability between various packages in order to achieve different design flows.
* tools for embedded design and to provide support for ARM as a secondary architecture in Fedora.
* tool set for Openmoko development and other opensource hardware communities.
* a Peer Review Web-based solution coupled with Eclipse IDE for Embedded/Digital Hardware IP design.
* PLA tools, C-based design methodologies, simulators for 8051 and 8085 microcontrollers and many more ...
FEL live CD can be downloaded here..
NOR Flash Memory:
NOR-type Flash memories are based on technologies that evolved largely from the first non-volatile memory technologies. They are typically organized as a number of blocks between 16 Kbytes and 128 Kbytes, each of which can be individually erased or programmed. The architecture can be either uniform if all of the blocks are the same size or asymmetrical when the blocks vary in size. The array can be organized as a single piece of memory or split into dual or multiple banks, and in some cases, one block (called boot block) located at the top or the bottom of the address space, is dedicated to the storage of the boot code. NOR Flash memories usually have a random access for reading at byte/word level and sometimes a page access mode, allowing the reader to view an entire page of 2 to 4 words in one go. When very rapid read operations are required, the Flash memory is equipped with a burst read mode, which allows data to be transferred on every clock cycle.
Parallel and Serial Interface:
Parallel Access and Serial Access Parallel buses were primarily used to interface flash memories with microcontrollers and microprocessors through an address bus, a data bus and a control bus. By default, the term "Flash memory" refers to a parallel interface memory. The data bus can be organized as x8 bits, x16 bits or x32 bits. In some cases, address and data buses can be multiplexed. They are available in densities of up to 128 Mbits. Because of their rapid read times, Flash memories are traditionally used for basic code or code-plus-parameter storage where greater flexibility compared to EPROM is more important than the additional unit cost. More recently, they have pervaded many new applications where their key functions are to store both code and data. This was achieved by dual operations supported by dual or multiple bank architecture, which enable programming/erasing operations in one bank while reading from another bank. The serial bus is used to connect a Flash memory to a microcontroller or an ASIC equipped with a serial bus. Serial buses are input/output interfaces supporting a mixed address/data protocol. The serial bus connectivity reduces the number of interface signals required. For example, the SPI bus, the most popular serial bus for serial Flash memories, requires only 4 signals (data in, data out, clock and chip select) compared to 21 signals necessary to interface a 10-bit address parallel memory. As a result, the number of pins of the memory package (memory and bus master) is reduced, as is the number of PCB tracks. Consequently, a serial memory can fit into a smaller and less expensive package. However, serial Flash memories are available in lower densities than Flash memories. The communication throughput between serial Flash memory and master processor is lower than for traditional Flash memories. Consequently, the time to download code into the serial memory and execute it from the memory is longer. As a result, serial Flash memories are usually used for small code storage associated with a cache RAM. This is called a code shadowing architecture. The executable code is first programmed in the memory and it is write protected. After power-up, it is downloaded from memory to RAM from where it is executed by the master processor.
Flash memories can be electrically erased and it is not necessary to erase the whole memory array in order to store new data in part of it. Flash memory, EPROM and EEPROM devices all use the same basic floating gate mechanism to store data, but they use different techniques for reading and writing data.
In each case, the basic memory cell consists of a single MOS transistor (MOSFET) with two gates:
• control gate connected to the read/write control circuitry
• floating gate located between the control gate and the channel of the MOSFET(the part of the MOSFET through which electrons flow between the so-called
Source and Drain terminals).
In a standard MOSFET, a single Gate terminal controls the electrical resistance of the channel: electrical voltage applied to the gate controls how much current can flow between the Source and Drain. The MOSFETs used in non-volatile memories include a second gate that is completely surrounded by an insulating layer of silicon dioxide, i.e., it is electrically isolated from the rest of the circuitry. Because the floating gate is physically very close to the MOSFET channel, even a small electric charge has an easily detectable effect on the electrical behavior of the transistor. By applying appropriate signals to the control gate and measuring the change in transistor behavior, it is possible to determine whether there is an electrical charge on the floating gate. Because the floating gate is electrically isolated from the rest of the transistor, special techniques are required to move electrons to and from the floating gate.
One method is to fill the MOSFET channel with high-energy electrons by making a relatively high current pass between the drain and the source of the MOSFET. Some of these "hot" electrons have sufficient energy to cross the potential barrier between the channels and reach the floating gate. When the high current in the channel is removed, these electrons remain trapped in the floating gate. This is the method used to program the memory cells in EPROM and Flash memories. This technique, known as Channel Hot Electron (CHE) injection, can be used to load an electrical charge onto the floating gate, but does not provide a way to discharge it. EPROM technology achieves this by flooding the entire memory array with ultra-violet light; the high-energy light rays penetrate the chip structure and impart enough energy to the trapped electrons to allow them to escape from the floating gate.
The second method of moving a charge to a floating gate is the quantum mechanical effect known as tunneling. In this method electrons are removed from the floating gate by applying a voltage that is large enough to cause electrons to 'tunnel' across the insulating oxide layer to the source between the MOSFET control gate and the source or the drain. The number of electrons that can tunnel across an insulating layer in a given time depends on the thickness of the layer and the value of the applied voltage. To meet realistic voltage levels and erase-time constraints, the insulating layer must be very thin, typically 7nm (70 Angstroms).
EEPROM memories use tunneling to charge and discharge the floating gate according to the polarity of the applied tunneling voltage. A Flash memory can therefore be considered to be a memory device that is programmed like an EPROM and erased like an EEPROM, although there is much more to Flash technology than simply grafting the EEPROM erase mechanism onto EPROM technology.
The most important difference between EPROM and the other two processes lies in the thickness of the oxide layer that separates the floating gate from the source. In an EPROM, this is typically 20-25nm, but this is far too thick to allow tunneling to take place at an acceptable rate with a practical voltage level. For Flash memory, tunnel oxide thickness of around 10nm is required, and the quality of this oxide layer has a dramatic effect on the performance and reliability of the device. This is one of the reasons that relatively few semiconductor manufacturers have mastered Flash technology and even fewer have been able to reliably combine Flash technology and mainstream CMOS processes to build products such as microcontrollers with embedded Flash memory.
In the next post on this series, we will look at NAND, NOR, Parallel & Serial Flashes!
A baby aspirin-size brain sensor containing 100 electrodes, each thinner than a human hair, that connects to the surface of the motor cortex (the part of the brain that enables voluntary movement), registers electrical signals from nearby neurons, and transmits them through gold wires to a set of computers, processors and monitors. The goal is for patients with brain stem stroke, ALS, and spinal cord injuries to eventually be able to control prosthetic limbs directly form their brains.An earlier version of the BrainGate system helped a young tetraplegic named Matt Nagle control a mouse cursor and operate a very basic prosthetic hand. A 25-year-old locked-in patient named Erik Ramsey, who is participating in the only other FDA-approved clinical trial of a brain-computer interface. Ever since a car accident nine years ago, the only part of Erik's body that has been under his control has been his eyeballs, and even those he can only move up and down. The hope is that he might someday use his neural implant to control a digital voice:
When Erik thinks about puckering his mouth into an o or stretching his lips into an e, a unique pattern of neurons fires--even though his body doesn't respond. It's like flicking switches that connect to a burned-out bulb. The electrode implant picks up the noisy firing signals of about fifty different neurons, amplifies them, and transmits them across Erik's skull to two small receivers glued to shaved spots on the crown of his head. Those receivers then feed the signal into a computer, which uses a sophisticated algorithm to compare the pattern of neural firings to a library of patterns Kennedy recorded earlier. It takes about fifty milliseconds for the computer to figure out what Erik is trying to say and translate those thoughts into sound.Like the BrainGate sensor, Erik's neural implant was inserted into the motor cortex (in his case, the specific region that controls the mouth, lips, and jaw). But Erik's implant only has a single electrode, whereas the BrainGate has 100, which means it should, theoretically, be able to differentiate signals from a far greater number of neurons.
It sounds a little sci-fi at first, but it's not: RFID tags are powered by electrical signals converted from electromagnetic waves emitted by a nearby sensor machine, which is exactly how this system is said to work. The thing is, the amount of electricity involved here is tiny, and Nokia's system won't even have a base station—it'll draw from ambient electromagnetic waves, meaning Wi-Fi, cell towers and TV antennae. Nokia hopes to harvest about 50 milliwatts—not quite enough to sustain a phone, but enough to mitigate drain, and slowly charge a handset that's been switched off.
Current prototypes only gather about 5 milliwatts, which is essentially useless, and scientists and industry experts just don't see the technology maturing to the point that Nokia wants it to, at least in the near future. But the company's researchers are standing strong:
I would say it is possible to put this into a product within three to four years.
If you believe them, this is pretty exciting: maybe not as a primary charging mechanism, but as a battery extender. [Technology Review—Image from Technology Review]
Moore's original statement that transistor counts had doubled every year can be found in his publication "Cramming more components onto integrated circuits", Electronics Magazine 19 April 1965:
The complexity for minimum component costs has increased at a rate of roughly a factor of two per year ... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer.
Intel 8008 | Intel Pentium4
The success and failure of high risk computer developments can quite often be traced to a single individual. It is not accidental that unique persons such as Gene Amdahl, Seymour Cray, Fred Brooks, and Bob Barton have become recognized leaders in the computer architecture and design field. Their reputations did not arise from a happy coincidence of being associated with a successful project; rather, they stand out because of their ability to generate a system wide concept, determine a course of action to get it implemented, make the necessary tradeoffs and finally drive through all obstacles to ensure completion of their vision.
Also read: Which Machines Do Computer Architects Admire?
Checkout the other lectures in the same category.
* Latest GuideWare™ methodology improvements for better productivity
* New Atrenta Console™ interface for improved ease of use (demo included)
* CDC Setup Manager (demo included)
* Multi-mode timing coverage report, including why it's valuable
* New at-speed test analysis
* CPF and UPF support
Title:SpyGlass 4.2.0 Webinar
Date:Wednesday, May 6, 2009
Time:7:00 PM - 8:00 PM PDT
After registering you will receive a confirmation email containing information about joining the Webinar.
Space is limited.Reserve your Webinar seat now at: https://www1.gotomeeting.com/register/439111672
Pitch: Musical notes as in "Do Re Me So .." or "Sa Re Ga Ma .." usually start from low pitch to high pitch.
Volume: How loud can you be.
Tone: The character/Timbre of sound. (Eg. The Rustle of Paper or the Tinkle of glass.
Pace: The speed of conversation or how long a sound lasts.
The variation of the above aspects of your voice give personality, variety and clarity to your conversation. To check and modulate the individual effectiveness of your voice focus attention by following the below steps...
1. Cup your right hand around your right ear pulling it forward.
2. Cup your left hand around your mouth to direct sound in to you ear.
3. Then talk and hear your voice. This is pretty much how people will hear you.
Use the below to control your voice..(the PAMPERS of voice if i may call it ;-))
Effective communications skills for the Industry - Being Politically ccorrect
Effective communications skills for the Industry - The Basics
Effective communications skills for the Industry - Introduction
A similar effort that was launched in France is the Design & Reuse (D&R) web portal which provides a secure catalog of 15,000 IP products from 150 suppliers with 37,000 registered users making 100,000 page views per month. D&R also sells a comprehensive intranet reuse infrastructure that provides an IP supply chain delivering external IPs as well as internal IPs from the designer site to the user site under the control of an IP management system hosting the corporate IP directory. For additional information, D&R
SIPAC, System Integration & Intellectual Property Authoring Center, is a non-profit organization located in South Korea that has an IP trading system providing a variety of IP related services. SIPAC has developed IP related guidelines for HDL coding and AMS design. It has also produced a web-based IP verification and evaluation system. For additional information SIPAC
Taiwan SoC Consortium (formerly named the Silicon IP Consortium) is a non-profit organization. Member companies include fabless design houses, integrated devices manufacturers, system vendors, foundries, EDA companies, design service companies and semiconductor research organizations. Its primary mission is to facilitate IP information sharing and IP exchange, especially for the companies in Taiwan. For additional information, TaiwanSoC
The Open SystemC Initiative (OSCI) is an independent not-for-profit organization composed of a broad range of companies, universities and individuals dedicated to supporting and advancing SystemC as an open source standard for system-level design.
The specific purposes of this organization include:
1. Building a rich system-level design language and open source implementation based on C++ class libraries, called "SystemC",
2. Encouraging availability and adoption of intellectual property (IP), tools and methodologies based on SystemC,
3. The mechanisms that enable the continued growth of the SystemC community,
4. Defining interoperability criteria for IP and tools based on SystemC, (5) delivering updates to the SystemC Language Reference Manual (LRM) and open source implementation, and
6. The SystemC language via the IEEE.
The open source proof-of-concept SystemC 2.1 library and the transaction-level modeling (TLM) library have been updated.
Success stories from ST Microelectronics, Intel, IBM, QualComm, Texas Instruments and Conexant which were given in session 22 of the 2004 Design Automation Conference and can be accessed at: DAC
One of the major benefits of SystemC is the ability to model at the transaction level (TLM), where the use of simple function calls in communication modeling brings gains in both coding productivity and simulation speed. The TLM standard is now here and is being adopted. The OSCI TLM interface standard extends the practical value of the SystemC class library by providing a standard modeling kit for the construction of TLM interfaces, thus reducing the work needed to construct new interfaces and increasing the opportunities for interopability. At the same time, the release of version 2.1 of the SystemC class library has added new features which extend the utility of SystemC for
transaction level modelling.
A SystemC specification of the AMBA bus is now available free of charge. The specification is a fully cycle-accurate representation of the AMBA AHB protocol including the AHB-lite protocol that is widely adopted for high-performance bus-matrix architectures. The AMBA specification is an established, open methodology that serves as a framework for SoC designs, effectively providing the interconnect that binds IP cores together. The specification has been downloaded by more than 12,000 design engineers and implemented in hundreds of ASIC designs. The AMBA AHB cycle-level modeling specification is available now for download from: AMBA
Synthesis of SystemC can be performed using the Agility Compiler from Celoxica. The compiler synthesizes SystemC directly to high-density FPGA and programmable SoC logic and generates RTL VHDL and Verilog for SoC design. SoC designers using SystemC can maintain the C level of design abstraction throughout the entire SystemC design process while taking advantage of simulation speeds that are orders of magnitude faster than RTL. Thus, whole systems can now be verified using the same test-bench at all stages of the design process.
Forte Design Systems offers a Cynthesizer, a synthesis tool that delivers an implementation path from SystemC to RTL, verification, and co-simulation. Cynthesizer accelerates RTL delivery for leading-edge integrated circuits and systems-on-chip by automatically generating optimized RTL code from a C++ / SystemC algorithmic description. It can also be used to explore architectural trade-offs, e.g. area and performance. Significant productivity and quality-of-results improvements are being realized. For additional information, access: ForteDS
CoWare, Inc. has partnered with Forte to provide the first integrated SystemC-based solution for electronic system-level (ESL) design to implementation. The tight integration of CoWare's SystemC-based ConvergenSC system-on-chip (SoC) design tools and Forte's Cynthesizer SystemC behavioral synthesis product unites system architecture, simulation, and synthesis in a first-of-its kind flow. Users can explore and validate a design's system architecture in CoWare's ConvergenSC, then synthesize to RTL using Forte's Cynthesizer, and verify the RTL in a system context with the same SystemC model.
CoWare has also integrated its SPW digital signal processing application design tool with the Cadence Virtuoso custom design platform enabling wireless product design teams to reduce schedule risk through an evolutionary change of their methodology. SPW reference models have been instrumental in the successful tapeout of thousands of wireless designs to-date. The new flow enables broader reuse of the reference models for the RF and analog designer's benefit. By using SPW reference models throughout different design domains, wireless design teams can dramatically increase design efficiency and reduce risk. Starting from the SPW frontend, users can select the parts of the system that are used as the reference or testbench, and mark them for export. SPW automatically creates an optimized simulation model with interfaces based on SystemC signals and data types. SPW was enhanced with technology from the CoWare ConvergenSC platform design tool. Cadence's Virtuoso platform leverages the same SystemC technology based on the Cadence/CoWare technology alliance, readily importing the newly created SPW model. RF designers do not need to be familiar with SPW to benefit from the new flow. For additional information, access: CoWare
CoWare provides its tools to universities via its university program UniversityProgram@CoWare.com). For U.S. universities, there is no charge for ConvergenSC and LISATek and up to 300 licenses of SPW can be obtained for an annual fee of $500. For European universities and non-profit research, CoWare participates in the EUROPRACTICE program.
In India, IIT Delhi and IIT Kharagpur use ConvergenSC and LISATek to support courses on system level modeling, system synthesis and architecture design space exploration.
Free SystemC On-line Tutorial
The Leela Palace Kempinski, Bangalore
The Grand Ballroom
Bangalore, India 560 008
Conference Date: July 9-10, 2009
Apr 20, 2009, Preliminary Acceptance Notification
May 11, 2009, Final Paper Due
May 15, 2009, Final Acceptance Notification and Presentation Spots Awarded
Jun 15, 2009, Draft Slides Due
Jun 16-26, 2009, Dry Run Practice at Synopsys
Jun 29, 2009, Final Slides Due
Jul 9-10, 2009, SNUG India 2009 Conference
About SNUG: SNUG is an open forum that provides Synopsys users worldwide with a unique opportunity to exchange ideas, discuss problems and explore solutions. In addition to a highly technical program that focuses on real-world design challenges, each SNUG event includes interaction with Synopsys executives, product developers and applications consultants about future product directions and product and support quality. Each SNUG is driven by a local Technical Committee, with operational support provided by Synopsys.
There are currently 11 SNUG conferences held around the world (most are held annually):
* North America (San Jose and Boston)
* Europe (Munich and Israel)
* Asia Pacific (lndia, Taiwan, Singapore, Korea and China)
* Japan (Tokyo and Osaka)
The SMARTi UEmicro is a single chip 2G/3G CMOS RF transceiver for the low end segment of the 3G market. It is a cost down version of the proven and widely adopted SMARTi UE with a backward compatible hard- and software interface via DigRF v3.09. With the elimination of external Low Noise Amplifiers (LNA’s) and a simplified co-banded RF frontend without Rx filters SMARTi UEmicro is perfectly matching the mass market requirements for ultra low cost 3G handsets. SMARTi UEmicro delivers exceptional RF performance for up to three of the globally used WCDMA bands plus Dual- or Quad-Band GSM/EDGE at lowest system cost.
This groundbreaking technology will enable ubiquitous mobile communications coverage from anywhere in North America using mass-market devices costing about the same as terrestrial cellular-only devices. SDR-enabled satellite-terrestrial handsets will operate with multiple cellular and satellite-based communications technologies including GSM, GPRS, EDGE, WCDMA, HSDPA, HSUPA and GMR1-2G/3G. We are very happy to contribute our innovative SDR technology to this exciting new application of integrated satellite-terrestrial mobile devices in both SkyTerras and TerreStars networks, said Ronen Ben-Hamou, Vice President and General Manager of Software Defined Radio mobile platforms in the Wireless Division of Infineon. Together with our partners we leverage the flexibility and efficiency of our SDR technology into this connected-anywhere mobile environment, enabling operators to provide very compelling multi-standard communication devices to even the most demanding end users.
We are very pleased to work with Infineon on the development of an SDR-based chipset platform, said Drew Caplan, Chief Network Officer for SkyTerra. With this agreement, we are taking another significant step toward making combined satellite-terrestrial communications a reality for consumers, enterprise, government and public safety users. We anticipate that this SDR chipset agreement will expand our marketopportunities as well as the range of technologies and potential devices that will be satellite-terrestrial capable, providing consumers with additional cost-effective purchase options. Dennis Matheson, Chief Technology Officer at TerreStar, added: The Infineon SDR chipset is a tremendous addition to our chipset program and greatly expands the universe of devices that will be satellite enabled. In addition, the programmable nature of SDR technology allows for feature upgrades via software and shortest-ever turn-around times for nextgeneration products. We look forward to using this chipset platform to perform additional handset trials on our evolving 4G network. To enable satellite connectivity in the SDR platform, Infineon will integrate GMR1-3G technology furnished by Hughes Network Systems, a market leader for mobile satellite solutions.
About the XMM SDR 200
Infineons SDR mobile platform, called XMM SDR 200, requires only one single baseband device, the X-GOLD SDR 20 and one single RF transceiver, a member of Infineons leading SMARTi family. As X-GOLD SDR 20 also includes all power management functions on-chip, less than half the number of key components are needed compared to previous modem solutions. This platform enables satellite-terrestrial terminals in a small form factor comparable to todays cellular-only mobile phones. The XMM SDR 200 is an extremely cost- and energy-efficient solution, requiring only one dedicated chipset for the two distinct standards. With this platform, Infineon once again demonstrates its capability to provide semiconductor solutions that connect people and increase energy efficiency in electronic devices. First platform samples will be available in Q3 of 2009.
Microelectronics Systems News, will be in the format of a Newsletter that includes items of interest in the areas of IC design, prototyping, micorelectronic systems including embedded systems and programmable system-on-chip platforms using FPGAs.
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Updated to get the links here in this same post!!!
- APLAC - A flexible analog circuit simulation and design tool!
- Berkeley's Design Technology Warehouse
- Cirrus: CAD System for Rtl Design, Circuit Design, Tool integration
- Disydent: Digital system design environment
- Event Controlled Systems Project
- Free HDL: A project to develop a free, open source, GPL'ed VHDL simulator for Linux!
- iEDISON3: Statistical design and optimization of circuits
- ILLIADS2: Fast Timing Simulator for MOS VLSI Circuits
- Magic Layout System
- MISTIC TCAD: Michigan Synthesis Tools for IC's
- Mosis: Electric
- Nemesis: A program that simulates and generates test patterns for circuits with a variety of different types of faults
- p2m : A GIMP plug-in for converting image files into formats that are compatible with integrated circuit and printed circuit board layout tools!
- POSE: Power Optimization and Synthesis Environment
- ProperCAD: Parallel algorithms for VLSI CAD applications
- Research in VLSI Circuit Testing, Verification, and Diagnosis
- SPICECAD: The Schematic Entry for SPICE3,HSPICE and TITAN under X11 R5/R6
- Stanford TCAD: Development of Computer-Aided Design for more than two decades!
- Static Free Soft
- The Chipmunk System
- The Olympus synthesis system (More info needed!)
- XRLCAD -- A C++ library for manipulating Calma (GDS) and CIF libraries
1. African American or Afro-American (Blacks/Negroes)
2. Chairperson (Chairman)
3. Ms. (instead of Miss/Mrs)
4. Mentally challenged (Mentally retarded)
5. Economically Challenged (Poor)
6. Vertivally challenged (Short)
7. Visual equipement and support (Instead of Visual Aids, now has the H.I.V disease connotation - A negative association)
There are many words like these and the above list is just a hint..
Effective communications skills for the Industry - The Basics
Effective communications skills for the Industry - Introduction
Date:Tuesday, March 31, 2009
Time: 11 amPT / 2 pm ET
Register now @:
Liveattendees who also submit the feedback form will be eligible to win a FREE 8GBiPod Touch (value approx. $250).
Accelerating Time-to-SI –Closure:
Unmanagedtiming-ECOs during the final stages of design can severely impact your tapeout schedule. Join our experts to learn how to usesignoff-driven SI-closure to keep your schedule on track and your performanceon target. This is the first in IC Compiler 2009 Webinar Series highlightingkey technologies for speeding design closure. Up-coming topics includeplacement-congestion minimization, power-rail design and in-design physicalverification.
Dr. Henry Sheng
Dr. Henry Sheng is R&D Group Director for Design Closure in ICCompiler. Henry and his organization are responsible for implementationextraction, timing and signal integrity, as well as Multi-corner Multi-mode(MCMM) and post-route closure. He has been with Synopsys since 1996. Henryholds a Ph.D. degree in Electrical Engineering and Computer Science from theUniversity of California, Berkeley.
Dr. Jinan Lou
Dr. JinanLou received his B.S. degree in Computer Engineering and Computer Science, M.S.and Ph.D. degrees in Computer Engineering, from University of SouthernCalifornia, Los Angeles, in 1993, 1995 and 1999, respectively. He is currentlya Principal Engineer at Synopsys. His research interests include physicaloptimization, layout driven logic synthesis and post-layout optimization fordeep-submicron technologies.
IEEE Symposium on Low-Power and High Speed Chips
April 15-17, 2009
COOL Chips is an International Symposium initiated in 1998 to present advancement of low-power and high-speed chips. The symposium covers leading-edge technologies in all areas of microprocessors and their applications. The COOL Chips XII is to be held in Yokohama on April 15-17, 2009, and is targeted at the architecture, design and implementation of chips with special emphasis on the areas listed below. The COOL Chips Organizing Committee will ask the MICRO to publish selected papers in a special issue on COOL Chips XII.
Contributions are solicited in the following areas:
* Low Power-High Performance Processors for Multimedia, Digital Consumer Electronics, Mobile, Graphics, Encryption, Robotics, Networking and Biometrics.
* Novel Architectures and Schemes for Single Core, Multi-Core, Embedded System, Reconfigurable Computing, Grid, Ubiquitous, Dependable Computing and Wireless.
* Cool Software including Binary Translations, Compiler Issues and Low Power Techniques.
1. Be very clear in your thought and be prepared about what you want to say.
2. Be aware of high risk situations and know what you don't want to say.
3. Be confident, but not very confident.
4. Understand what is needed of the discussion.
5. Always do your homework while understanding the product or service.
6. Listen diligently! This applies for both verbal and non-verbal communication.
7. Always ask searching questions to show you are interested.
8. Be clear in matter while trying to keep it short and simple.
9. Be sensitive to others.
a. Talk politely.
b. Be courteous.
10. Keep a positive attitude while using positive and accurate language.
11. Be genuinely convinced and enthusiastic.
a. Verbal communication and body language should communicate the same message.
12. Be very clear in speech.
Extra verbal - Should convey correct meaning!
Intra verbal - Use appropriate voice modulation to adjust pitch and speed.
13. Pick up the signals early.
Signals can be Confusion, Resentment, Disinterest, Skepticism, Pre-Occupation, Objection, Anger etc.
14. Never assume things. Ask and Listen.
15. People like to be liked - This is the Human factor.
16.Always address the person by name and try to recall likes and dislikes.
17. Offer a choice of things!
18. Use words to express and not impress.
The next big step is in controlling communication through probing techniques!
Probe to identify needs, concerns or views. Here needs can be satisfied to achieve objectives and to further or add value to your service or brand. Concerns and views have to be empathized about and addressed.
There are two kind of probes that can be used as tools to achive the above target...
1, Open probe
2, Closed probe
An open probe is one question that may have an elaborate answer. An example would be "What are the critical concerns and priorities in your business?". Open probes can be used encourage customers to speak freely about a topic of their choice.
A closed probe is one that has a a very short answer. An example would be "Will you be paying by cash or card?". These can be used to control and direct the communication.
When open probes don't work, closed probes can be chosen from prospected information in observation or clues the customer gives during meetings or any other teleconferences.
Effective communications skills for the Industry - Introduction
There is indeed a very important factor in the lack of traction for open-source in EDA. They are the engineers. Engineers who have both domain expertise and skills to make a meaningful contribution to any sophisticated EDA tool are relatively very small. Even if they did, all of them are already working either for EDA giants or for internal tools groups at other big semiconductor firms that have strict employment agreements. It is possible that most of these specialized people aren’t particularly free to contribute to an open source EDA in their “personal” free time.
I would really appreciate your comments and opinions on this important Topic.
With the April 1, 2009 H-1B visa application process start date just weeks away, reports from the Valley suggest that even though the number of US ...
The following series is my humble attempt to share my views on effective communication from my past experiences of working in a multi-cultural and cross site setting, spanning various geographic zones. This will be more general that can be applied to any industry rather than just Electronics or Semiconductors!
The following are the topics i will be writing about and i hope to get your valuable feedback. If you feel that i should talk about some specific topic please leave a comment and i will address that.
Being Politically Correct
How to be Assertive?
When to be Aggressive?
Customization for various kinds of people
Analyzing Body Language
Effective Email Communications
Cultural Scenarios - US, British, German, Chinese, Indian
Importance of Feedback - One size will not fit all!
Social Etiquettes & Diversity
What to know who i am? Then explore me on Blogger or LinkedIn!
On Tuesday, March 31, 2009 5:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco)
Panelist(s) Info: Krishna Balachandran, Director of Low Power Verification Marketing, Srikanth Jadcherla, Group R&D Director, Janick Bergeron, Synopsys Fellow
Duration: 1 hour
Description: Power management and low power design bring a whole new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path in the delivery of the chip, now needs to take on additional tests and flows to ensure that the power management scheme is functional.
The complexity of power management and the broad spectrum of design scenarios could easily lead to escaped bugs without a rigorous methodology in place. In this webinar, we will focus first on the complexities and changes brought about in the low power era and the bugs types that are new to low power design. We will then cover the process of rigorous verification for low power and present a structured and reusable methodology for low power. The webinar will highlight the VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs. All the concepts covered in this webinar are detailed in the recently published "Verification Methodology Manual for Low Power" (VMM-LP), which customers of Synopsys can download in a PDF form from www.vmmcentral.org/vmmlp.
Following the presentation, a formal Q&A will take place.
Look at the following block. This is the most common building in any FPGA. It is called a Logic Element(LE) by Altera and Configurable Logic Element(CLB) by Xilinx. The structure may not be accurate but illustrates the idea behind it.
We estimate the number of FPGA cells required for a design by counting the number of flip-flops and primary inputs that are in the fanin of each flip-flop. Only flip-flops count, because combinational signals are collapsed into the circuity within an FPGA cell. The circuitry for any flip-flop signal with up to four source flip-flops can be implemented on a single FPGA cell. If a flip-flop signal is dependent upon five source flip-flops, then two FPGA cells are required.
This technique is generally an overestimate, because a single cell can drive several other cells (common sub expression elimination).
Coming to the Question...
Map the combinational circuits below onto generic FPGA cells. You could explain in words on how you could achieve this or send me an email. Appreciate your comments. Based on the solution received, i will post the answers here later! Good luck!
Wednesday, 18th March:
Custom Processor / Programmable Accelerator Design and Implementation.
Tuesday, 31st March:
Getting Started with Virtual Platforms: A Software Developer Perspective.
Wednesday, 8th April:
Challenges for LTE Wireless Systems Design.
These webinars will also be recorded for viewing it later as per participant’s convenience.
Here are the details of the Webinars with the registration link:
Wednesday, March 18, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Drew Taussig
Custom Processor / Programmable Accelerator Design and Implementation
As companies are looking to improve their competitive advantage, the need for programmable hardware accelerators, ASIPs and custom processors is growing rapidly. They provide the solution to performance and flexibility challenges electronic system designers are facing today. But, in today s economy where there are fewer resources and everyone has cost reduction on their mind, how can you design them efficiently? How can you generate efficient RTL? How can you equip the software developers with the right linker, assembler, compiler, simulator and debugger?
What you will learn:
* Concepts and reasons behind developing custom processors and hardware programmable accelerators.
* Design and implementation steps and how these steps can be streamlined using efficient and powerful design tools that automate the exploration, RTL implementation and software development tools.
* How the generated processor can be used for development and verification in a Virtual Platform for Software Development, an FPGA or an RTL emulation environment.
Tuesday, March 31, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Achim Nohl
Getting Started with Virtual Platforms: A Software Developer Perspective
The ability to debug and analyze software defects efficiently is a key requirement in order to complete a software project successfully and on time. Especially when porting legacy software such as an OS or migrating sequential code to multi-core platforms, powerful debugging tools and methods are indispensable. This one hour webinar gives a technical overview and various practical examples on the usage of virtual platforms for debugging. Virtual platforms enable a whole new world of software analysis and debugging solutions. An OS-aware software analysis framework eases the understanding of the history and interaction between multiple parallel software stacks. The controllability and visibility of virtual platforms enables engineers to trigger and analyze multi-processing defects such as dead-locks and race conditions. Correctness and performance of complex shared-memory communication, task scheduling and control can be asserted which results in a significant quality and productivity gain for the software engineer.
What you will learn:
* Overview of the debugging infrastructure provided by a virtual platform
* Practical examples for applying virtual platforms for embedded software debugging based on real world software and hardware configurations
* How the OS-aware analysis and debug framework can be used and customized to debug typical problems that appear during OS porting
* How domain integration problems in an asymmetric, multi-processing platform can be identified
* How virtual platforms can be used to debug shared memory communication problems based on a multi-core video driver
* How virtual platforms can be used to spot an existing bug in the Linux kernel for the ARM11 MPcore configuration
Wednesday, April 8, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Dr. Johannes Stahl
Challenges for LTE Wireless Systems Design
Long-Term Evolution (LTE) wireless systems have 5-10x higher processing complexity than currently-deployed 3G wireless systems. This creates a unique pressure across all aspects of the handsets, the basestation and the network. Previous product platforms have to be significantly re-architected and entirely new software applications have to be developed to take advantage of the much higher bandwidth that LTE is targeted to provide. In this webinar, we will explain those design challenges and offer different approaches that design teams can take to deliver advanced products. The webinar targets development managers across the supply chain that are developing LTE products today or are planning to get involved in the near future. Whether you are a manager inside a network operator, basestation or handset OEM or you are in a semiconductor company, you should participate and learn about how you can meet your LTE product roll-out schedule within your tight development budgets.
What you will learn:
* How network operators can leverage the LTE standard to optimize their network throughput
* How chip architects will extract maximum application performance from their architectures
* How programmability of signal processing accelerators does not come at the expense of too much power
* How application or baseband processing software is developed if it is spread across multiple processor cores
ASIC technology can give a performance improvement of up to threefold and can be always compared with the same functions being executed in software. Over the past decade, ASIC technology has seen major changes or improvements in density and performance driven by the smaller processes of the silicon. Now a days Most of the Major Companies involved in developing the ASIC's solution targeting from 65nm to 45nm technology.
The ASIC verification plays a vital role in proving that the Product is tested in all modes of functionality. To Address the issue of ASIC verification customer will tend make use language construct like VHDL/Verilog for modeling the RTL behavior and High Level Verification Language construct like specman 'e' language or System-Verilog which will help in modeling BFM and as well as generating the scenarios either in Random or Constrained manner.
Well, all sounds good and cheesy as said! Claims were made that the proposed bailout was the need of the hour and that it was needed very badly and a failure to do so will turn the economic crisis into a catastrophe. But one question everyone had was the moral dilemma that faced the Congress and the White house in the question that if the recipients of the stimulus package should continue to outsource jobs :-). The main objective of the bailout plan was in the creation of jobs for Americans.
Will American citizens only be the sole benefactor of the bailout package? Outsourcing companies outside the U.S. including here in India and the Philippines benefited from the demand of manpower for jobs in consumer services like jobs in research, bill payment and collection, credit analysis and investment banking. The logical conclusion was that companies should be allowed freedom to manage as what they may deem good for their business. Every outsourcing company cannot possibly take all the jobs that a U.S. company requires.
In an era where companies need to stay competitive, not to earn big but just to survive, outsourcing can complement the operations of a company as it is an efficient way to run the company’s operations. The first step a troubled company takes is to save money and instantaneously reduce cost. A company should compare their operations to their competitors to see exactly what is lacking and continuously adapt. There are issues that the stimulus package is not a debate on protectionism and taxpayers are not served well with the continuing export of jobs by the very companies that need the bailout package. The jobs from financial institutions that are in the center of attention are in research, banking and back office.
Meanwhile, President Obama is also aware that revolutions in communication and technology has sent jobs to any place in the world with Internet connection and according to him the fact that the world is more competitive cannot be reversed. Outsourcing of American jobs overseas cannot be reversed and U.S. workers need to compete for jobs with other people on the other side of the globe. This is how globalization is defined. The government must invest in research and innovation to create jobs and industries as the country’s problems on economic front cannot be overcome by building protectionist walls.
In contrast what is speculated to happen in the next couple of months is that, the H1-B's will be laid off in the U.S. This laid off workforce, will be re-hired in India to a great extent in the coming months due to outsourcing by the U.S firms.
Lets wait and see how much the U.S can manage without the H1-B's in general.
Today there is a generation of us in the indian workforce, totally unfamiliar with layoffs, and totally unfamiliar with the idea that a job is actually 100% insecure.
The good news about this is that there is not a huge difference between someone laid off and someone not laid off in that all of us feel vulnerable, scared and cheated in some ways.
Which also means that some etiquette has to be followed in that it is different than it used to be for talking to someone who’s been laid off.
1. Never ask "how's the job hunt?" Because the job hunt doesn't change much from day to day, but it's far more demoralizing to report that in someones face.
2. Ask about things like hobbies, kids, and their health – all interesting topics to talk about.
3. Talk about the current affairs & industry news in general - Tell the person what you're working on. Trends you're hearing about. Personnel shifts you've seen. Also, gossip counts as news. Workplace gossip is a positive way to bond. Forget what your mom told you about gossip being bad karma. In this case, gossip equals good karma.
4. Offer atleast one good contact - You need not pretend that connecting in LinkedIn or facebook is going to help his cause, because he should have been building the network long before the layoff loomed. But you could offer up one person you know well who could talk with the person.
5. Acknowledge trouble with the significant other - On this is tricky! More men are getting laid off than women, which puts women in a bad spot because most women choose a husband thinking he'll earn more. Today it's a fair game, and even compassionate to acknowledge.
6. Don't be shy of gratitude - Tell a co-worker who’s been laid off that you miss him or her. And what you miss. It's hard to keep up morale when you're looking for a job. And so often we forget what we are talented at because rejection makes us feel totally un-talented.
The SaaS and Cloud Computing Roundtable will be held from 6:30 - 8:00 pm on Wed Feb 25th in the Monterey/Carmel rooms at the San Jose Doubletree Hotel. This is immediately following the DVCon reception down the hall, so grab a drink and a bite and then wander on over.
The format will consist of 5 brief (presentations from people involved in various perspectives in SaaS and cloud computing for EDA: