Webinar watch: Accelerating Time-To-SI-Closure


Webinar:Accelerating Time-To-SI-Closure
Date:Tuesday, March 31, 2009
Time: 11 amPT / 2 pm ET
Duration: 60Minutes

Register now @:
http://TIG.cmptechnetwork.com/cgi-bin4/DM/y/eA0KLkvJ0A0HEhi0Ez

Liveattendees who also submit the feedback form will be eligible to win a FREE 8GBiPod Touch (value approx. $250).

Accelerating Time-to-SI –Closure:
Unmanagedtiming-ECOs during the final stages of design can severely impact your tapeout schedule. Join our experts to learn how to usesignoff-driven SI-closure to keep your schedule on track and your performanceon target. This is the first in IC Compiler 2009 Webinar Series highlightingkey technologies for speeding design closure. Up-coming topics includeplacement-congestion minimization, power-rail design and in-design physicalverification.

Presenters:
Dr. Henry Sheng
Dr. Henry Sheng is R&D Group Director for Design Closure in ICCompiler. Henry and his organization are responsible for implementationextraction, timing and signal integrity, as well as Multi-corner Multi-mode(MCMM) and post-route closure. He has been with Synopsys since 1996. Henryholds a Ph.D. degree in Electrical Engineering and Computer Science from theUniversity of California, Berkeley.

Dr. Jinan Lou
Dr. JinanLou received his B.S. degree in Computer Engineering and Computer Science, M.S.and Ph.D. degrees in Computer Engineering, from University of SouthernCalifornia, Los Angeles, in 1993, 1995 and 1999, respectively. He is currentlya Principal Engineer at Synopsys. His research interests include physicaloptimization, layout driven logic synthesis and post-layout optimization fordeep-submicron technologies.

Upcoming VLSI/IC Conference - Cool Chips 2009


Cool Chips 2009
IEEE Symposium on Low-Power and High Speed Chips
Yokohama, Japan
April 15-17, 2009

COOL Chips is an International Symposium initiated in 1998 to present advancement of low-power and high-speed chips. The symposium covers leading-edge technologies in all areas of microprocessors and their applications. The COOL Chips XII is to be held in Yokohama on April 15-17, 2009, and is targeted at the architecture, design and implementation of chips with special emphasis on the areas listed below. The COOL Chips Organizing Committee will ask the MICRO to publish selected papers in a special issue on COOL Chips XII.

Contributions are solicited in the following areas:

* Low Power-High Performance Processors for Multimedia, Digital Consumer Electronics, Mobile, Graphics, Encryption, Robotics, Networking and Biometrics.
* Novel Architectures and Schemes for Single Core, Multi-Core, Embedded System, Reconfigurable Computing, Grid, Ubiquitous, Dependable Computing and Wireless.
* Cool Software including Binary Translations, Compiler Issues and Low Power Techniques.

Effective communications skills for the Industry - The Basics


In any conversation you have to lay some ground rules that can setup a platform to project your thoughts. These are some of the basics that you cannot afford to miss.. (not in any order)

1. Be very clear in your thought and be prepared about what you want to say.
2. Be aware of high risk situations and know what you don't want to say.
3. Be confident, but not very confident.
4. Understand what is needed of the discussion.
5. Always do your homework while understanding the product or service.
6. Listen diligently! This applies for both verbal and non-verbal communication.
7. Always ask searching questions to show you are interested.
8. Be clear in matter while trying to keep it short and simple.
9. Be sensitive to others.
a. Talk politely.
b. Be courteous.
10. Keep a positive attitude while using positive and accurate language.
11. Be genuinely convinced and enthusiastic.
a. Verbal communication and body language should communicate the same message.
12. Be very clear in speech.
Extra verbal - Should convey correct meaning!
Intra verbal - Use appropriate voice modulation to adjust pitch and speed.
13. Pick up the signals early.
Signals can be Confusion, Resentment, Disinterest, Skepticism, Pre-Occupation, Objection, Anger etc.
14. Never assume things. Ask and Listen.
15. People like to be liked - This is the Human factor.
16.Always address the person by name and try to recall likes and dislikes.
17. Offer a choice of things!
18. Use words to express and not impress.



The next big step is in controlling communication through probing techniques!
Probe to identify needs, concerns or views. Here needs can be satisfied to achieve objectives and to further or add value to your service or brand. Concerns and views have to be empathized about and addressed.

There are two kind of probes that can be used as tools to achive the above target...
1, Open probe
2, Closed probe

An open probe is one question that may have an elaborate answer. An example would be "What are the critical concerns and priorities in your business?". Open probes can be used encourage customers to speak freely about a topic of their choice.

A closed probe is one that has a a very short answer. An example would be "Will you be paying by cash or card?". These can be used to control and direct the communication.

When open probes don't work, closed probes can be chosen from prospected information in observation or clues the customer gives during meetings or any other teleconferences.

Earlier post:
Effective communications skills for the Industry - Introduction

Open-Source EDA Tools - No supporters?


Why is there a lack of usable open-source tools in the commercial EDA industry? The academic world has many tools to boast of but not many are industry worthy! Hypothetically, all the best software tools in the world should be Open-Source due to the kind of collaboration that can be leveraged from all the smart brains the industry can offer. Why is it not happening like other software specific applications?Why isn't there a IBM or SUN in the EDA world that can do what these two did to the software world? Why Synopsys and Cadence are shying away from these burning questions? Is it a matter of time this may happen due to the current state of the global economy or is it due to the present state of industry consolidation which may rule out any scope all together? As a matter of fact, when Google hires it engineers it looks at what open source projects the candidate has worked on during his free time! Do we have a pioneer who can think in these terms? Can Mentor Graphics or others start this trend?

There is indeed a very important factor in the lack of traction for open-source in EDA. They are the engineers. Engineers who have both domain expertise and skills to make a meaningful contribution to any sophisticated EDA tool are relatively very small. Even if they did, all of them are already working either for EDA giants or for internal tools groups at other big semiconductor firms that have strict employment agreements. It is possible that most of these specialized people aren’t particularly free to contribute to an open source EDA in their “personal” free time.

I would really appreciate your comments and opinions on this important Topic.

H-1Bs: Should US visa policies adjust in this economy?


With the April 1, 2009 H-1B visa application process start date just weeks away, reports from the Valley suggest that even though the number of US ...

Effective communications skills for the Industry - Introduction


Communications skills play a very vital role in today's competitive business environment. It is also critical in a core technical environment where the success of your product or service will depend on how effectively you communicate and share your ideas and opinions.

The following series is my humble attempt to share my views on effective communication from my past experiences of working in a multi-cultural and cross site setting, spanning various geographic zones. This will be more general that can be applied to any industry rather than just Electronics or Semiconductors!

The following are the topics i will be writing about and i hope to get your valuable feedback. If you feel that i should talk about some specific topic please leave a comment and i will address that.
The Basics
Being Politically Correct
Modulation skills
Paradigms
Effective Teleconferencing
Listening Skills
How to be Assertive?
When to be Aggressive?
Customization for various kinds of people
Analyzing Body Language
Effective Email Communications
Presentation Skills
Cultural Scenarios - US, British, German, Chinese, Indian
Importance of Feedback - One size will not fit all!
Social Etiquettes & Diversity


What to know who i am? Then explore me on Blogger or LinkedIn!

Webinar Watch - Synopsys, A Structured Methodology for Verifying Low Power Designs


An in-depth technical webinar focusing on low power verification methodology.

On Tuesday, March 31, 2009 5:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco)
Panelist(s) Info: Krishna Balachandran, Director of Low Power Verification Marketing, Srikanth Jadcherla, Group R&D Director, Janick Bergeron, Synopsys Fellow
Duration: 1 hour
Description: Power management and low power design bring a whole new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path in the delivery of the chip, now needs to take on additional tests and flows to ensure that the power management scheme is functional.

The complexity of power management and the broad spectrum of design scenarios could easily lead to escaped bugs without a rigorous methodology in place. In this webinar, we will focus first on the complexities and changes brought about in the low power era and the bugs types that are new to low power design. We will then cover the process of rigorous verification for low power and present a structured and reusable methodology for low power. The webinar will highlight the VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs. All the concepts covered in this webinar are detailed in the recently published "Verification Methodology Manual for Low Power" (VMM-LP), which customers of Synopsys can download in a PDF form from www.vmmcentral.org/vmmlp.

Register Now!

Following the presentation, a formal Q&A will take place.

Free E-Books Download - RSS Subscribers Only!


Subscribe to our RSS Feeds to download your copy of the E-Book.
E-Book: The Digital Signal Processing Handbook. Read further to find out how!

To download this and future E-Book's, please look at the bottom of the post in your preferred RSS reader. See example below!

Interview Question


It has been a while since we posted any puzzles or interview questions to tickle everyone's teeny brains. Recession has hit us in a big way and there seems to be a running drought in originality of the interview questions asked now-a-days. Even the ones shared on the various blogs that have cropped up these days are either ruthlessly copied or "massaged". Dont you think so? So to say, that while keeping the spirit or creativity and intelligence alive and hoping that the recession passes without much a casualty here is one next in line to our trend of Original Interview Questions. Hurray!

Look at the following block. This is the most common building in any FPGA. It is called a Logic Element(LE) by Altera and Configurable Logic Element(CLB) by Xilinx. The structure may not be accurate but illustrates the idea behind it.

We estimate the number of FPGA cells required for a design by counting the number of flip-flops and primary inputs that are in the fanin of each flip-flop. Only flip-flops count, because combinational signals are collapsed into the circuity within an FPGA cell. The circuitry for any flip-flop signal with up to four source flip-flops can be implemented on a single FPGA cell. If a flip-flop signal is dependent upon five source flip-flops, then two FPGA cells are required.

This technique is generally an overestimate, because a single cell can drive several other cells (common sub expression elimination).

Coming to the Question...

Map the combinational circuits below onto generic FPGA cells. You could explain in words on how you could achieve this or send me an email. Appreciate your comments. Based on the solution received, i will post the answers here later! Good luck!






List of VLSI & IC Conferences and Workshops


CoWare upcoming webinars!


CoWare the leading global supplier of platform-driven electronic system-level (ESL) design software and services is arranging a series of online Webinars based on Processor Design, Software Development and Wireless Design to benefit the user. The webinars will be held on the following dates:

Wednesday, 18th March:
Custom Processor / Programmable Accelerator Design and Implementation.

Tuesday, 31st March:
Getting Started with Virtual Platforms: A Software Developer Perspective.

Wednesday, 8th April:
Challenges for LTE Wireless Systems Design.

These webinars will also be recorded for viewing it later as per participant’s convenience.

Here are the details of the Webinars with the registration link:
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Wednesday, March 18, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Drew Taussig

Custom Processor / Programmable Accelerator Design and Implementation
As companies are looking to improve their competitive advantage, the need for programmable hardware accelerators, ASIPs and custom processors is growing rapidly. They provide the solution to performance and flexibility challenges electronic system designers are facing today. But, in today s economy where there are fewer resources and everyone has cost reduction on their mind, how can you design them efficiently? How can you generate efficient RTL? How can you equip the software developers with the right linker, assembler, compiler, simulator and debugger?

What you will learn:
* Concepts and reasons behind developing custom processors and hardware programmable accelerators.
* Design and implementation steps and how these steps can be streamlined using efficient and powerful design tools that automate the exploration, RTL implementation and software development tools.
* How the generated processor can be used for development and verification in a Virtual Platform for Software Development, an FPGA or an RTL emulation environment.

Register now!

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Tuesday, March 31, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Achim Nohl

Getting Started with Virtual Platforms: A Software Developer Perspective
The ability to debug and analyze software defects efficiently is a key requirement in order to complete a software project successfully and on time. Especially when porting legacy software such as an OS or migrating sequential code to multi-core platforms, powerful debugging tools and methods are indispensable. This one hour webinar gives a technical overview and various practical examples on the usage of virtual platforms for debugging. Virtual platforms enable a whole new world of software analysis and debugging solutions. An OS-aware software analysis framework eases the understanding of the history and interaction between multiple parallel software stacks. The controllability and visibility of virtual platforms enables engineers to trigger and analyze multi-processing defects such as dead-locks and race conditions. Correctness and performance of complex shared-memory communication, task scheduling and control can be asserted which results in a significant quality and productivity gain for the software engineer.

What you will learn:
* Overview of the debugging infrastructure provided by a virtual platform
* Practical examples for applying virtual platforms for embedded software debugging based on real world software and hardware configurations
* How the OS-aware analysis and debug framework can be used and customized to debug typical problems that appear during OS porting
* How domain integration problems in an asymmetric, multi-processing platform can be identified
* How virtual platforms can be used to debug shared memory communication problems based on a multi-core video driver
* How virtual platforms can be used to spot an existing bug in the Linux kernel for the ARM11 MPcore configuration

Register now!

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Wednesday, April 8, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Dr. Johannes Stahl

Challenges for LTE Wireless Systems Design
Long-Term Evolution (LTE) wireless systems have 5-10x higher processing complexity than currently-deployed 3G wireless systems. This creates a unique pressure across all aspects of the handsets, the basestation and the network. Previous product platforms have to be significantly re-architected and entirely new software applications have to be developed to take advantage of the much higher bandwidth that LTE is targeted to provide. In this webinar, we will explain those design challenges and offer different approaches that design teams can take to deliver advanced products. The webinar targets development managers across the supply chain that are developing LTE products today or are planning to get involved in the near future. Whether you are a manager inside a network operator, basestation or handset OEM or you are in a semiconductor company, you should participate and learn about how you can meet your LTE product roll-out schedule within your tight development budgets.

What you will learn:
* How network operators can leverage the LTE standard to optimize their network throughput
* How chip architects will extract maximum application performance from their architectures
* How programmability of signal processing accelerators does not come at the expense of too much power
* How application or baseband processing software is developed if it is spread across multiple processor cores

Register now!

e-language using Random generation approach


Specman e-language powered by random generation concept. specman e-language is an HVL (High Level Verification Language) and an IEEE standard language used for constructing complex verification Environments. ‘e’ code written can never execute stand-alone without the Specman tool. The primary purpose of Specman e-language verification environment is to find more complex bugs for a given DUT (VHDL/Verilog) rather than using Test benches written in Verilog or VHDL. Test benches written using ‘e’ language run on Random approach using the built in pseudo random mechanism and as well executed using Constrained Random approach!

SOC verification


At a Glance, an ASIC (Application Specific Integrated Circuit) can consolidate the work of many chips into a single, smaller, faster package reducing the manufacturing and support costs while boosting the speed of the device built with this technology. ASIC technology is so advanced that many functions traditionally implemented in software can be migrated into ASIC's functionality. More specifically, ASIC let designers think in terms of Hardware Design connectivity and use the power of constantly improving silicon technology to improve the timing and build devices targeted to specific functions like wireless or consumer electronics domain.

ASIC technology can give a performance improvement of up to threefold and can be always compared with the same functions being executed in software. Over the past decade, ASIC technology has seen major changes or improvements in density and performance driven by the smaller processes of the silicon. Now a days Most of the Major Companies involved in developing the ASIC's solution targeting from 65nm to 45nm technology.

The ASIC verification plays a vital role in proving that the Product is tested in all modes of functionality. To Address the issue of ASIC verification customer will tend make use language construct like VHDL/Verilog for modeling the RTL behavior and High Level Verification Language construct like specman 'e' language or System-Verilog which will help in modeling BFM and as well as generating the scenarios either in Random or Constrained manner.