Effective communications skills for the Industry - Modulation skills


During a conversation voice modulation plays a major role in defining the atmosphere to get the message out. In this post we look at the various factors that can be worked during a conversation.

Pitch: Musical notes as in "Do Re Me So .." or "Sa Re Ga Ma .." usually start from low pitch to high pitch.
Volume: How loud can you be.
Tone: The character/Timbre of sound. (Eg. The Rustle of Paper or the Tinkle of glass.
Pace: The speed of conversation or how long a sound lasts.

The variation of the above aspects of your voice give personality, variety and clarity to your conversation. To check and modulate the individual effectiveness of your voice focus attention by following the below steps...

1. Cup your right hand around your right ear pulling it forward.
2. Cup your left hand around your mouth to direct sound in to you ear.
3. Then talk and hear your voice. This is pretty much how people will hear you.

Use the below to control your voice..(the PAMPERS of voice if i may call it ;-))
P Projection
A Articulation
M Modulation
P Pronunciation
E Enunciation
R Repetition
S Speed


Earlier post:
Effective communications skills for the Industry - Being Politically ccorrect
Effective communications skills for the Industry - The Basics
Effective communications skills for the Industry - Introduction

Virtual Component Websites and Software


Virtual Component Exchange (VCX) is a web-based, regulated trading exchange for semiconductor virtual components or intellectual property (IP). The exchange was established as an outgrowth of the Alba Centre which was launched in 1997 by an economic development agency of the Scottish government. The main elements of the Alba Centre initiative were the Virtual Component Exchange, the Institute for System Level Integration and the development of the Alba Campus, the physical embodiment of the Alba vision. The Virtual Component Exchange has been acquired by Beach Solutions which continues to operate the website and to sell database solutions to both IP buyers and sellers. For additional information, VCX

A similar effort that was launched in France is the Design & Reuse (D&R) web portal which provides a secure catalog of 15,000 IP products from 150 suppliers with 37,000 registered users making 100,000 page views per month. D&R also sells a comprehensive intranet reuse infrastructure that provides an IP supply chain delivering external IPs as well as internal IPs from the designer site to the user site under the control of an IP management system hosting the corporate IP directory. For additional information, D&R

SIPAC, System Integration & Intellectual Property Authoring Center, is a non-profit organization located in South Korea that has an IP trading system providing a variety of IP related services. SIPAC has developed IP related guidelines for HDL coding and AMS design. It has also produced a web-based IP verification and evaluation system. For additional information SIPAC

Taiwan SoC Consortium (formerly named the Silicon IP Consortium) is a non-profit organization. Member companies include fabless design houses, integrated devices manufacturers, system vendors, foundries, EDA companies, design service companies and semiconductor research organizations. Its primary mission is to facilitate IP information sharing and IP exchange, especially for the companies in Taiwan. For additional information, TaiwanSoC

OpenFPGA


OpenFPGA is an emerging effort to foster and accelerate the adoption and incorporation of reconfigurable computing based computing solutions in high-performance computing and enterprise application environments. OpenFPGA will foster shared and open efforts to address challenges of portability, interoperability and intra-application communication for FPGA and reconfigurable applications in high-performance and enterprise computing environments.

Free Chip Estimation Tool


A free design automation tool for chip estimation has been developed by Giga Scale IC, Inc. The tool named "InCyte" estimates IC die size, power, leakage, yield, and cost, enabling designers to visualize both the technical and economic impacts of their design specification. The tool's rapid "what-if" analysis makes it easy for designers to visualize tradeoffs between key design metrics, and across technology nodes and process variants. Users can generate accurate and optimized chip estimates at the architectural stage of the design process, resulting in significantly shorter design times and lower design costs.

Teaching Embedded Systems using ARM and FPGAs


Prof. Saeid Nooshabadi of the University of New South Wales in Sydney, Australia, has an excellent website describing his course and the accompanying laboratory-based exercises. Emphasis is placed on interfacing the ARM processor to other programmable hardware devices. Students use GNU tools operating under Linux to compile and simulate C, C++ and assembly-language programs. FPGA development is performed using Xilinx ISE WebPack and ModelSim-XE operating under Microsoft Windows. Click for additional information!

Guides for Writing and Presentations and References


Top 500 Supercomputers


A list of the Top 500 performing supercomputers is available at: Top 500. Since 1993, the list has been updated twice a year to indicate the best performance on the Linpack benchmark. Except for one machine which uses Microsoft Windows, all of the top 500 machines employ either the Linux or Unix operating system.

SystemC


SystemC provides hardware-oriented constructs within the context of C++ as a class library implemented in standard C++. Its use spans design and verification from concept to implementation in hardware and software. SystemC provides an interoperable modeling platform which enables the development and exchange of very fast system-level C++ models. It also provides a stable platform for development of system-level tools.

The Open SystemC Initiative (OSCI) is an independent not-for-profit organization composed of a broad range of companies, universities and individuals dedicated to supporting and advancing SystemC as an open source standard for system-level design.

The specific purposes of this organization include:
1. Building a rich system-level design language and open source implementation based on C++ class libraries, called "SystemC",
2. Encouraging availability and adoption of intellectual property (IP), tools and methodologies based on SystemC,
3. The mechanisms that enable the continued growth of the SystemC community,
4. Defining interoperability criteria for IP and tools based on SystemC, (5) delivering updates to the SystemC Language Reference Manual (LRM) and open source implementation, and
6. The SystemC language via the IEEE.

The open source proof-of-concept SystemC 2.1 library and the transaction-level modeling (TLM) library have been updated.
Access: SystemC

Success stories from ST Microelectronics, Intel, IBM, QualComm, Texas Instruments and Conexant which were given in session 22 of the 2004 Design Automation Conference and can be accessed at: DAC

One of the major benefits of SystemC is the ability to model at the transaction level (TLM), where the use of simple function calls in communication modeling brings gains in both coding productivity and simulation speed. The TLM standard is now here and is being adopted. The OSCI TLM interface standard extends the practical value of the SystemC class library by providing a standard modeling kit for the construction of TLM interfaces, thus reducing the work needed to construct new interfaces and increasing the opportunities for interopability. At the same time, the release of version 2.1 of the SystemC class library has added new features which extend the utility of SystemC for
transaction level modelling.

A SystemC specification of the AMBA bus is now available free of charge. The specification is a fully cycle-accurate representation of the AMBA AHB protocol including the AHB-lite protocol that is widely adopted for high-performance bus-matrix architectures. The AMBA specification is an established, open methodology that serves as a framework for SoC designs, effectively providing the interconnect that binds IP cores together. The specification has been downloaded by more than 12,000 design engineers and implemented in hundreds of ASIC designs. The AMBA AHB cycle-level modeling specification is available now for download from: AMBA

Synthesis of SystemC can be performed using the Agility Compiler from Celoxica. The compiler synthesizes SystemC directly to high-density FPGA and programmable SoC logic and generates RTL VHDL and Verilog for SoC design. SoC designers using SystemC can maintain the C level of design abstraction throughout the entire SystemC design process while taking advantage of simulation speeds that are orders of magnitude faster than RTL. Thus, whole systems can now be verified using the same test-bench at all stages of the design process.

Forte Design Systems offers a Cynthesizer, a synthesis tool that delivers an implementation path from SystemC to RTL, verification, and co-simulation. Cynthesizer accelerates RTL delivery for leading-edge integrated circuits and systems-on-chip by automatically generating optimized RTL code from a C++ / SystemC algorithmic description. It can also be used to explore architectural trade-offs, e.g. area and performance. Significant productivity and quality-of-results improvements are being realized. For additional information, access: ForteDS

CoWare, Inc. has partnered with Forte to provide the first integrated SystemC-based solution for electronic system-level (ESL) design to implementation. The tight integration of CoWare's SystemC-based ConvergenSC system-on-chip (SoC) design tools and Forte's Cynthesizer SystemC behavioral synthesis product unites system architecture, simulation, and synthesis in a first-of-its kind flow. Users can explore and validate a design's system architecture in CoWare's ConvergenSC, then synthesize to RTL using Forte's Cynthesizer, and verify the RTL in a system context with the same SystemC model.

CoWare has also integrated its SPW digital signal processing application design tool with the Cadence Virtuoso custom design platform enabling wireless product design teams to reduce schedule risk through an evolutionary change of their methodology. SPW reference models have been instrumental in the successful tapeout of thousands of wireless designs to-date. The new flow enables broader reuse of the reference models for the RF and analog designer's benefit. By using SPW reference models throughout different design domains, wireless design teams can dramatically increase design efficiency and reduce risk. Starting from the SPW frontend, users can select the parts of the system that are used as the reference or testbench, and mark them for export. SPW automatically creates an optimized simulation model with interfaces based on SystemC signals and data types. SPW was enhanced with technology from the CoWare ConvergenSC platform design tool. Cadence's Virtuoso platform leverages the same SystemC technology based on the Cadence/CoWare technology alliance, readily importing the newly created SPW model. RF designers do not need to be familiar with SPW to benefit from the new flow. For additional information, access: CoWare

CoWare provides its tools to universities via its university program UniversityProgram@CoWare.com). For U.S. universities, there is no charge for ConvergenSC and LISATek and up to 300 licenses of SPW can be obtained for an annual fee of $500. For European universities and non-profit research, CoWare participates in the EUROPRACTICE program.

In India, IIT Delhi and IIT Kharagpur use ConvergenSC and LISATek to support courses on system level modeling, system synthesis and architecture design space exploration.

Free SystemC On-line Tutorial
Access: SCOTT

Most Significant Papers on IC Test


Many important papers have been presented at the annual International Test Conference (ITC) over the past 35 years. The best of these are on-line at ITC Papers.

Configurable Multiprocessor Systems


Multiple microprocessor cores which communicate via an on-chip network are increasingly found in integrated circuit designs. These systems offer unprecedented levels of performance, while still remaining highly programmable and consuming modest amounts of power. In addition to high-end CPUs, they are highly suitable for high-performance embedded applications including multimedia, digital signal processing and networking. Dr. Steve Guccione of Cmpware, Inc., presented an invited paper at ERSA-2005 on this topic. His paper and slides are on-line as well as a free development kit at: Cmpware

Pirated EDA software available on Bangalore streets


We all know the severity of software piracy in Taiwan & China. But how many of you know that EDA software like Modelsim, Synopsys DC, etc sell on Bangalore streets in India for as low as Rs.25!!!! For the matter of fact, the slumdog who is selling the pirated software in question is not even aware that he is one. The CD is disguised as one of the Recent Bollywood or Hollywood hits. Cops just extort some money and leave him to continue his business!!!

Sponsored Link: Data Acquisition Devices for $579 USD or Less


National Instruments offers more than 300 world-class data acquisition devices starting as low as $99. Select from USB, Ethernet, Wi-Fi and PCI low-cost DAQ devices offering analog input, analog output, digital I/O, or multifunction I/O. All devices ship with free LabVIEW Signal Express LE data acquisition software. View specs and pricing.

SNUG India 2009: Dates to remember


Conference Location:
The Leela Palace Kempinski, Bangalore
The Grand Ballroom
Airport Road
Bangalore, India 560 008


Conference Date: July 9-10, 2009

Mar 2-Apr 3, 2009, Call for Papers
Apr 20, 2009, Preliminary Acceptance Notification
May 11, 2009, Final Paper Due
May 15, 2009, Final Acceptance Notification and Presentation Spots Awarded
Jun 15, 2009, Draft Slides Due
Jun 16-26, 2009, Dry Run Practice at Synopsys
Jun 29, 2009, Final Slides Due
Jul 9-10, 2009, SNUG India 2009 Conference

About SNUG: SNUG is an open forum that provides Synopsys users worldwide with a unique opportunity to exchange ideas, discuss problems and explore solutions. In addition to a highly technical program that focuses on real-world design challenges, each SNUG event includes interaction with Synopsys executives, product developers and applications consultants about future product directions and product and support quality. Each SNUG is driven by a local Technical Committee, with operational support provided by Synopsys.

There are currently 11 SNUG conferences held around the world (most are held annually):
* North America (San Jose and Boston)
* Europe (Munich and Israel)
* Asia Pacific (lndia, Taiwan, Singapore, Korea and China)
* Japan (Tokyo and Osaka)

Link Exchange


Sorry, we only Link-Exchange with Electronics, Semiconductors and ASIC/VLSI websites and Blogs!

Infineon introduces two RF-chips for LTE and 3G


Infineon has introduced two RF-chips for LTE and 3G - SMARTi LU for highest data rates with LTE, and SMARTi UEmicro for low cost 3G devices.SMARTi LU is a highly integrated 2G/3G/LTE multi-mode RF transceiver compliant to 3GPP Rel.7 and Rel.8. It supports up to six 3G and LTE Bands simultaneously with Quad Band GSM/EDGE. Its long feature list includes LTE FDD class 4 (up to 150Mbps downlink, 50Mbps uplink) MIMO Rx diversity (2Rx + 1Tx), HSPA+, HSPA, WCDMA and GSM/GPRS/EDGE. The device is supporting the global spread of HSPA/LTE spectrum throughout a wide variety of bands. With its MIPI DigRF v4 compliant high-speed digital Baseband interface, SMARTi LU sets a milestone towards “all digital” implementation and enables the silicon intensive baseband chips to follow a faster shrink path towards smaller technology nodes such as 32nm and below. SMARTi LU is based on a standard 65nm CMOS technology provided by multiple semiconductor foundries.

The SMARTi UEmicro is a single chip 2G/3G CMOS RF transceiver for the low end segment of the 3G market. It is a cost down version of the proven and widely adopted SMARTi UE with a backward compatible hard- and software interface via DigRF v3.09. With the elimination of external Low Noise Amplifiers (LNA’s) and a simplified co-banded RF frontend without Rx filters SMARTi UEmicro is perfectly matching the mass market requirements for ultra low cost 3G handsets. SMARTi UEmicro delivers exceptional RF performance for up to three of the globally used WCDMA bands plus Dual- or Quad-Band GSM/EDGE at lowest system cost.

Silicon Brain


Researchers have built a chip with the equivalent of 200,000 neurons and 50 million synapses in an effort to mimic a human brain in silicon.

Although the chip has a fraction of the number of neurons or connections found in a brain, its design allows it to be scaled up, says Karlheinz Meier, a physicist at Heidelberg University, in Germany, who has coordinated the Fast Analog Computing with Emergent Transient States project, or FACETS. A neuron circuit typically consists of about 100 components, while a synapse requires only about 20. However, because there are so much more of them, the synapses take up most of the space on the wafer, says Karlheinz.

Worlds First Satellite-Cellular Mobile Platform Based on SDR Technology


Infineon Technologies, SkyTerra, and TerreStar Networks today jointly announced the worlds first multi-standard mobile platform based on Infineons innovative software-defined-radio (SDR) technology. SkyTerra and TerreStar are both developing next-generation integrated satellite-terrestrial communications networks.

This groundbreaking technology will enable ubiquitous mobile communications coverage from anywhere in North America using mass-market devices costing about the same as terrestrial cellular-only devices. SDR-enabled satellite-terrestrial handsets will operate with multiple cellular and satellite-based communications technologies including GSM, GPRS, EDGE, WCDMA, HSDPA, HSUPA and GMR1-2G/3G. We are very happy to contribute our innovative SDR technology to this exciting new application of integrated satellite-terrestrial mobile devices in both SkyTerras and TerreStars networks, said Ronen Ben-Hamou, Vice President and General Manager of Software Defined Radio mobile platforms in the Wireless Division of Infineon. Together with our partners we leverage the flexibility and efficiency of our SDR technology into this connected-anywhere mobile environment, enabling operators to provide very compelling multi-standard communication devices to even the most demanding end users.

We are very pleased to work with Infineon on the development of an SDR-based chipset platform, said Drew Caplan, Chief Network Officer for SkyTerra. With this agreement, we are taking another significant step toward making combined satellite-terrestrial communications a reality for consumers, enterprise, government and public safety users. We anticipate that this SDR chipset agreement will expand our marketopportunities as well as the range of technologies and potential devices that will be satellite-terrestrial capable, providing consumers with additional cost-effective purchase options. Dennis Matheson, Chief Technology Officer at TerreStar, added: The Infineon SDR chipset is a tremendous addition to our chipset program and greatly expands the universe of devices that will be satellite enabled. In addition, the programmable nature of SDR technology allows for feature upgrades via software and shortest-ever turn-around times for nextgeneration products. We look forward to using this chipset platform to perform additional handset trials on our evolving 4G network. To enable satellite connectivity in the SDR platform, Infineon will integrate GMR1-3G technology furnished by Hughes Network Systems, a market leader for mobile satellite solutions.

About the XMM SDR 200
Infineons SDR mobile platform, called XMM SDR 200, requires only one single baseband device, the X-GOLD SDR 20 and one single RF transceiver, a member of Infineons leading SMARTi family. As X-GOLD SDR 20 also includes all power management functions on-chip, less than half the number of key components are needed compared to previous modem solutions. This platform enables satellite-terrestrial terminals in a small form factor comparable to todays cellular-only mobile phones. The XMM SDR 200 is an extremely cost- and energy-efficient solution, requiring only one dedicated chipset for the two distinct standards. With this platform, Infineon once again demonstrates its capability to provide semiconductor solutions that connect people and increase energy efficiency in electronic devices. First platform samples will be available in Q3 of 2009.

400th Post: Microelectronics Systems News!


Starting today we will be embarking on a new series called Microelectronics Systems News!
Microelectronics Systems News, will be in the format of a Newsletter that includes items of interest in the areas of IC design, prototyping, micorelectronic systems including embedded systems and programmable system-on-chip platforms using FPGAs.

This Newsletter will be broadcast to over 4000+ existing subscribers throughout the world. There is no charge for this service.

To make a contribution, send email to Murugavel Ganesan at: murugavelganesan@gmail.com
To be added to the email notification list, subscribe using feedburner using the link in the main page.
To be deleted, follow the instructions on feedburner!
For a change of address, just add the new address and then delete the old one.

Shareware VLSI CAD/CAE/EDA Software!


Checkout our Shareware VLSI CAD/CAE/EDA Software! section below to benefit from the numerous tools the Academic community has to offer. We will be updating as quite often as possible as we find more tools. Please comment to share the links you have found that will be of interest here. We really appreciate your support.

Updated to get the links here in this same post!!!

Effective communications skills for the Industry - Being politically correct!


Being politically correct is to being sensitive to people, their cultures with the evolving environment and society! Here are some examples.. The words in brackets should be avoided during conversations...!!!!


1. African American or Afro-American (Blacks/Negroes)
2. Chairperson (Chairman)
3. Ms. (instead of Miss/Mrs)
4. Mentally challenged (Mentally retarded)
5. Economically Challenged (Poor)
6. Vertivally challenged (Short)
7. Visual equipement and support (Instead of Visual Aids, now has the H.I.V disease connotation - A negative association)

There are many words like these and the above list is just a hint..


Earlier post:
Effective communications skills for the Industry - The Basics
Effective communications skills for the Industry - Introduction