Seven Steps to Success in Graduate School and Beyond


This is a list of essential skills that all successful researchers have developed. Without these skills, you cannot expect to succeed in research. If you fully develop your abilities in each of these areas, you will lay a strong foundation for the rest of your research career that will lead directly to success in research. The responsibility for the development of these skills is entirely your own

Clock network design


Clock network is usually formed by top-level mesh/network and bottom-level Steiner minimum trees. The objective of clock network design is 1.) minimum or bounded skew, 2.) minimum delay, 3.) bounded process variation. Can we compare different clock topologies, or, how can we evaluate the effectiveness of clock boosters and feedback loops?

IR drop driven placement


The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to place high current cells towards the periphery in a peripheral i/o design. Simple way to implement this is to have a fixed dummy block at the center of the chip and attach fake nets from it to cell instances in a DEF file. A commercial placer can then be used to place this netlist. After placement, fake blocks and nets can be deleted. This can lead to IR drop reduction.

Clock skew variation estimation


Clock meshes are used in state-of-the-art designs to construct clock routing in contrast to clock trees in older design. This shift in clock tree construction methodology is motivated by the fact that meshes cope better with variability effects. How do you use SPICE simulations to measure the skew of tree routing versus grid clock routing while taking variability effects into consideration. Can you extend your study to non-tree routings, i.e., clock trees with added short cuts? Also can you include delay comparison between tree and non-tree structures?

Impact of dummy fill on timing


How can you quantify the impact of dummy fill on post-layout timing?  Dummy fill can be inserted into a layout using SOC Encounter or post-tape-out tools like Calibre/Assura. You should then extract dummy fill using Fire-n-Ice extractor and compare pre-fill and post-fill timing. Can you compare the impact of filling approaches (grounded vs. floating)?

The effect of whitespace and aspect ratio on wirelength and timing


Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever studied the impact of whitespace (and aspect ratio) on timing and wirelength, by say increasing the whitespace from 0% to 100% and evaluate the impact on both wirelength and timing. Can you predict how this will look like? For a 300 mm wafer, can you parameterize the relationship between the number of dies produced, timing, die aspect ratio, wirelength and whitespace?

Investigation on timing analysis inaccuracies


Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, manufacturing variation, etc. are very common. How do you tackle them in real life designs? How do you do it using Prime Time (PT)?

Distributions in statistical timing


How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final design timing distributions. How do you implement a simple statistical timer by (say) 500 Monte Carlo runs of STA (e.g. Primetime). Assume independent gate delays. Assume gate-delay distributions and generate circuit delay distributions. Delays can be changed in the SDF file. Interconnect may be ignored. Can we try tem for a few probability distributions (e.g. Gaussian, asymmetric Gamma, Triangular, etc).

Effect of WLM and target frequency on performance


How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?

Dynamic power supply


Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage according to data path criticality. You are asked to take a testcase and upgrade its power supply network to dynamic power supply. How can you verify the power reduction of your technique?

Clock tree theory


Constructing a zero-skew clock tree can be formulated as constructing a path-length balanced tree (assuming path delay is proportional to path length), i.e., to have identical path length between the root and any leave of the tree. The problem can be in a Euclidean plane, a rectilinear plane, or with other distance metrics. This problem's computation complexity is open. Can you find an approximation algorithm for the problem which guarantees a given error bound?

Statistical clock tree design


Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a statistical function. A rule of thumb for minimum process variation clock tree design is to have balanced branches, i.e., identical buffers from identical distances to the clock source, and symmetric clock routing branches with identical capacitive loads. Can you have a more flexible clock tree design scheme, while maintaining a minimized/bounded clock skew from a statistical point of view?

Randomized algorithm/approximation scheme for statistical timing analysis


Statistical timing analysis gives a distribution for signal delay at each node in a netlist. A Monte Carlo simulation can give discrete distribution functions. Can there be a randomized algorithm or approximation scheme for statistical timing analysis with guaranteed error bound?

Clock driver input alignment


Modern clock networks include several drivers in which delays are affected by the timing of their input signal transitions. How do you find out the input alignment of clock network drivers which leads to worst case driver gate delays?

Re-timing tackles long combinational logic paths


Re-timing reduces longest combinational logic paths by relocating some of the flip-flops, both logically and physically. How do you evaluate the effectiveness of re-timing, with existing tools and/or some of your own scripts? Comparing with useful clock skew is a plus.

Transistor level technology remapping


This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. This can be done algorithmically (e.g. pattern matching) or in an ad-hoc fashion. You can verify your area saving, timing improvement and power consumption reduction after this step.

Transistor sizing / multi-Vt design


This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further optimizing it. Optimization can be for example adjusting transistor widths, or assigning different transistor threshold voltages in a dual threshold voltage design. This can be done algorithmically (e.g. TILOS) or in an ad-hoc fashion. See how much timing improvement you get vs. just gate-level optimization. Also notice any "error" in STA methodology and highlight it further.  Following timing optimization, further optimize the design to reduce power  consumption without losing any timing.

Whip Your Resume Into Shape


Join Penelope Trunk TODAY, May 20, 8PM Eastern | 5PM Pacific, as she discusses the 3 most common mistakes that smart people make on their resumes. After attending this webinar you'll understand why the smartest people don't always get the best jobs. It's never a bad time to fine tune your resume.

Process variation extraction


Process variation extraction needs to be design specific, and based on random field simulation, as mechanical engineering techniquesStatistical timing analysis is based on a priori knowledge of process variations. The lack of such a priori knowledge of process variations prevents accurate statistical timing analysis and has been largely blamed for foundry confidentiality policy. In this paper, it is shown that a significant part of process variations are specific to the design, and can only be achieved based on production chip performance variabilities.

Interview with Anuj Valmiki, VLSI Design Manager


Anuj, who's worked on video chips for nearly 20 years, is a great role model for all practicing engineers. He's worked in multiple successful startups, thrived through several acquisitions into some of the largest semiconductor makers, as well as had a stint in the public sector. He's even taken a foray into EDA for system design and managed to fit in a sabbatical. Through all this he has stayed a hands-on designer, managing complex projects and continued to train and mentor younger designers. He brings a unique perspective on the success of Indian design and what engineers can learn from his own experience. Check out this interesting 3 part (Part1, Part2, Part3) interview at http://mahalowpower.com/ if you want to gather some inspiration!

Backend physical design Interview Questions


I have listed below a set of common interview questions asked mainly in interviews related to physical design or backend activities in ASIC or VLSI chip design process. Typically these interviews start with questions on physical design(PD) flow and goes on to deeper details.
* What is signal integrity? How it affects Timing?
* What is IR drop? How to avoid .how it affects timing?
* What is EM and it effects?
* What is floor plan and power plan?
* What are types of routing?
* What is a grid .why we need and different types of grids?
* What is core and how u will decide w/h ratio for core?


* What is effective utilization and chip utilization?
* What is latency? Give the types?
* What is LEF?
* What is DEF?
* What are the steps involved in designing an optimal pad ring?
* What are the steps that you have done in the design flow?
* What are the issues in floor plan?
* How can you estimate area of block?
* How much aspect ratio should be kept (or have you kept) and what is the utilization?
* How to calculate core ring and stripe widths?
* What if hot spot found in some area of block? How you tackle this?
* After adding stripes also if you have hot spot what to do?
* What is threshold voltage? How it affect timing?
* What is content of lib, lef, sdc?
* What is meant my 9 track, 12 track standard cells?
* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
* What is setup and hold? Why there are ? What if setup and hold violates?
* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
* How R and C values are affecting time?
* How ohm (R), fared (C) is related to second (T)?
* What is transition? What if transition time is more?
* What is difference between normal buffer and clock buffer?
* What is antenna effect? How it is avoided?
* What is ESD?
* What is cross talk? How can you avoid?
* How double spacing will avoid cross talk?
* What is difference between HFN synthesis and CTS?
* What is hold problem? How can you avoid it?
* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
* What is partial floor plan?
* What parameters (or aspects) differentiate Chip Design & Block level design??
* How do you place macros in a full chip design?
* Differentiate between a Hierarchical Design and flat design?
* Which is more complicated when u have a 48 MHz and 500 MHz clock design?
* Name few tools which you used for physical verification?
* What are the input files will you give for primetime correlation?
* What are the algorithms used while routing? Will it optimize wire length?
* How will you decide the Pin location in block level design?
* If the routing congestion exists between two macros, then what will you do?
* How will you place the macros?
* How will you decide the die size?


* If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
* If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
* In your project what is die size, number of metal layers, technology, foundry, number of clocks?
* How many macros in your design?
* What is each macro size and no. of standard cell count?
* How did u handle the Clock in your design?
* What are the Input needs for your design?
* What is SDC constraint file contains?
* How did you do power planning?
* How to find total chip power?
* How to calculate core ring width, macro ring width and strap or trunk width?
* How to find number of power pad and IO power pads?
* What are the problems faced related to timing?
* How did u resolve the setup and hold problem?
* If in your design 10000 and more numbers of problems come, then what you will do?
* In which layer do you prefer for clock routing and why?
* If in your design has reset pin, then it’ll affect input pin or output pin or both?
* During power analysis, if you are facing IR drop problem, then how did u avoid?
* Define antenna problem and how did u resolve these problem?
* How delays vary with different PVT conditions? Show the graph.
* Explain the flow of physical design and inputs and outputs for each step in flow.
* What is cell delay and net delay?
* What are delay models and what is the difference between them?
* What is wire load model?
* What does SDC constraints has?
* Why higher metal layers are preferred for Vdd and Vss?
* What is logic optimization and give some methods of logic optimization.
* What is the significance of negative slack?
* How the width of metal and number of straps calculated for power and ground?
* What is negative slack ? How it affects timing?
* What is track assignment?
* What is grided and gridless routing?
* What is a macro and standard cell?
* What is congestion?
* Whether congestion is related to placement or routing?
* What are clock trees?
* What are clock tree types?
* Which layer is used for clock routing and why?
* What is cloning and buffering?
* What are placement blockages?
* How slow and fast transition at inputs effect timing for gates?
* What is antenna effect?
* What are DFM issues?
* What is .lib, LEF, DEF, .tf?
* What is the difference between synthesis and simulation?
* What is metal density, metal slotting rule?
* What is OPC, PSM?
* Why clock is not synthesized in DC?
* What are high-Vt and low-Vt cells?
* What corner cells contains?
* What is the difference between core filler cells and metal fillers?
* How to decide number of pads in chip level design?
* What is tie-high and tie-low cells and where it is used

Insulting leadership practices


Here are five of the most insulting leadership practices, the ones that virtually guarantee a business will end up with the most self-esteem challenged, optionless team members when the dust settles.

RTL synthesis and other backend Interview Questions (with answers)


Q1: How would you speed up an ASIC design project by parallel computing? Which design stages can be distributed for parallel computing, which cannot, and what procedures are needed for maintaining parallel computing?
Ans: Mentioning the following important steps in parallel computing is essential:
1. Partitioning the design
2. Distributing partitioned tasks among multiple CPUs
3. Integrating the results


WHAT STAGES: The following answers are acceptable. Others may be accepted if you gave a reasonable explanation of why you can or cannot use parallel computing in a particular stage of the flow.
Can use parallel computing:
- Synthesis after partitioning
- Placement (hierarchical design)
- Detailed routing
- DRC
- Functional verification
- Timing Analysis (partition the timing graph)
Cannot use parallel computing:
- Synthesis before partitioning
- Floorplanning
- Flat Placement
- Global Routing
CONSTRAINTS: Mentioning that care must be taken to make sure that partition boundaries are consistent when integrating the results back together.

Q2: What kinds of timing violations are in a typical timing analysis report? Explain!
Ans: Acceptable answers...
- Setup time violations
- Hold time violations
- Minimum delay
- Maximum delay
- Slack
- External delay

Q3: List the possible techniques to fix a timing violation.
Ans: Acceptable answers...
- Buffering
Buffers are inserted in the design to drive a load that is too large for a logic cell to efficiently drive. If the net is too long then the net is broken and buffers are inserted to improve the transition which will ultimately improve the timing on data path and reduce the setup violation.
To reduce the hold violations buffers are inserted to add delay on data paths.- Mapping - Mapping converts primitive logic cells found in a netlist to technology-specific logic gates found in the library on the timing critical paths.
- Unmapping - Unmapping converts the technology-specific logic gates in the netlist to primitive logic gates on the timing critical paths.
- Pin swapping - Pin swapping optimization examines the slacks on the inputs of the gates on worst timing paths and optimizes the timing by swapping nets attached to the input pins, so the net with the least amount of slack is put on the fastest path through the gate without changing the function of the logic.
- Wire sizing
- Transistor (cell) sizing - Cell sizing is the process of assigning a drive strength for a specific cell in the library to a cell instance in the design.If there is a low drive strength cell in the timing critical path then this cell is replaced by higher drive strength cell to reduce the timing violation.
- Re-routing
- Placement updates
- Re-synthesis (logic transformations)

- Cloning - Cell cloning is a method of optimization that decreases the load of a very heavily loaded cell by replicating the cell. Replication is done by connecting an identical cell to the same inputs as the original cell.Cloning clones the cell to divide the fanout load to improve the timing.
- Taking advantage of useful skew
- Logic re-structuring/Transformation (w/Resynthesis) - Rearrange logic to meet timing constraints on critical paths of design
- Making sure we don't have false violations (false path, etc.)

Q4: Give the linear time computation scheme for Elmore delay in an RC interconnect tree.
Ans: The following is acceptable...
- Elmore delay formula
T = Sum over all nodes i in path (s,t) of Ri*Ci where Ci is the total capacitance in the sub tree rooted at node i, or alternatively, the sum over the capacitances at the nodes times the shared resistance between the path of interest and the path to the node.
- Explaining terms in formula
- Mentioning something that shows that it can be done in linear time ("lumped"
or "shared" resistances, "recursive" calculations, etc)

Q5: Given a unit wire resistance "r" and a unit wire capacitance "c", a wire segment of length "l" and width "w" has resistance "l/w" and capacitance "cwl". Can we reduce the Elmore delay by changing the width of a wire segment? Explain your answer.
Ans: You needed to mention that by scaling different segments by different amounts, you can reduce the delay (e.g. wider segments near the root and narrower segments near the leaves. Delay is independent of width because the "w" term cancels out.

Q6: Extend the ZST-DME algorithm to embed a binary tree such that the Elmore delay from the root to each leaf of the tree is identical.
Ans: You needed to mention that a new procedure is needed for calculating the Elmore delay assuming that certain merging points are chosen, instead of just the total downstream wire-length. The merging segment becomes a set of points with equal Elmore delay instead of just equal path length. You could refer the paper "Low-Cost Single-Layer Clock Trees With Exact Zero Elmore Delay Skew", Andrew B. Kahng and Chung-Wen Albert Tsao.

Q7: IPO (sometimes also referred to as "In-Place Optimization") tries to optimize the design timing by buffering long wires, resizing cells, restructuring logic etc.
Explain how these IPO steps affect the quality of the design in terms of area, congestion, timing slack.
(a) Why is this called "In-Place Optimization" ?
(b) Why are the two IPO steps different ?
(c) Why are both used ?

Ans: IPO optimizes timing by buffer insertion and cell resizing. Important steps that are performed in IPO include fixing {setup,hold} time, max. transition time violation. Timing slack along all arcs is optimized by these operations. Increase in area and reduction in timing slack depend upon timing and IPO constraints.
(a) This step is referred to as "In-Place Optimization" because IPO performs resizing and buffer in-place (between cells in the row). It does not perform placement optimization in this step.
(b) The first IPO1 step is performed after placement. It performs trial-route--> extraction --> timing analysis to determine the quality of placement. Setup and hold time fixing is done according to result of timing analysis. The second IPO step is performed after clock tree synthesis. CTS performs clock buffer insertion to balance skews among all flip-flops. IPO2 step optimizes timing paths between flip-flops taking the actual clock skew.
(c) If IPO2 step is not performed after CTS, then timing paths between flip-flops are not tuned for clock skew variation. Even though NanoRoute performs timing optimization, it is more of buffer insertion in long interconnect to fix setup and hold times.

Q8: Clocking and Place-Route Flow. Consider the following steps:
- Clock sink placement
- Standard-cell global placement
- Standard-cell detailed placement
- Standard-cell ECO placement
- Clock buffer tree construction
- Global signal routing
- Detailed signal routing
- Bounded-skew (balanced) clock (sub)net routing
- Steiner clock (sub)net routing
- Clock sink useful skew scheduling (i.e., solving the linear program, etc.)
- Post-placement (global routing based) static timing analysis
- Post-detailed routing static timing analysis
(a) As a designer of a clock distribution flow for high-performance standard-cell based ASICs, how would you order these steps? Is it possible to use some steps more than once, others not at all (e.g., if subsumed by other steps).
(b) List the criteria used for assessing possible flows.
(c) What were the 3 next-best flows that you considered (describe as variants of your flow), and explain why you prefer your given answer.

Ans:(a) My basic flow:
(1) SC global placement
(2) post-placement STA
(3) clock sink useful-skew scheduling
(4) clock buffer tree construction that is useful-skew aware (cf. associative skew.)
(5) standard-cell ECO placement (to put the buffers into the layout)
(6) Steiner clock subnet routing at lower levels of the clock tree (following CTGen type paradigm)
(7) bounded-skew clock subnet routing at all higher levels of the clock tree, and as necessary even at lower levels, to enforce useful skews
(8) global signal routing
(9) detailed signal routing,
(10) post-detailed routing STA
(b)Criteria:
(1) likelihood of convergence with maximum clock frequency
(2) minimization of CPU time (by maximizing incremental steps, minimizing .detailed. steps, and minimizing iterations)
(3) make a good trade-off between wiring-based skew control and wire cost (this suggests Steiner routing at lower levels, bounded-skew routing at higher levels).
[Comment 1. Criteria NOT addressed: power, insertion delay, variant flow for hierarchical clocking or gated clocking.
Comment 2: I do not know of any technology for clock sink placement that can separate this from placement of remaining standard cells. So, my flow does not invoke this step. I also don't want post-route ECOs.]
(c) Variants:
(1) introduce Step 11: loop over Steps 3-10 (not adopted because cost benefit ratio was not attractive, and because there is a trial placement + global routing to drive useful-skew scheduling, buffer tree construction and ECO placement);
(2) after Steps 1-4, re-place the entire netlist (global, detailed placement) and then skip Step 5 (not adopted because benefits of avoiding ECO placement and leveraging a good clock skeleton were felt to be small-buffer tree will largely reflect the netlist structure, and replacing can destroy assumptions made in Steps 3-4);
(3) can iterate the first 5 steps essentially by iterating: clock sink placement, (ECO placement for legalization), (incremental) standard-cell (global + detailed) placement (not adopted because I feel that any objective for standalone clock sink placement would be very "fuzzy", e.g., based on sizes of intersections of fan-in/fan-out cones of sequentially adjacent FFs)

Q9: If we migrate to the next technology node and double the gate count of a design, how would you expect the size of the LEF and routed DEF files to change? Explain your reasoning.
Ans: The LEF file will remain roughly the same size (same richness of cell library, say, between 500-1200 masters), modulo possible changes in conventions (e.g., CTLF used to be a part of LEF) and modulo possible additional library model semantics (e.g., adding power modeling into LEF). The DEF file should at least double (the components and nets will double, but if there is extra routing complexity (more complex geometries, and more segments per connection due to antenna rules or badly scaling router heuristics) the DEF could grow significantly faster.

Quantum chips will replace silicon chips anyways


Physicists at McGill University in the US now have a system where they can measure the energy involved in adding electrons to semiconductor nanocrystals, which are known as quantum dots.

The research team has built a 'cantilever force sensor' that can remove individual electrons that have been added to a quantum dot. The energy of this interaction can be measured. This is anticipated to be important in replacing the silicon chip. Currently computers work using processors containing transistors that are in either an on or off position - conducting versus nonconducting. With quantum computing, processors can work with many different states, which can both increase their speed and reduce their size. As scientists begin to understand these nanoscale systems, they can better predict and understand their electronic properties. "We are determining optical and electronic transport properties," said Dr. Peter Grütter, McGill's associate dean of research. This is essential for the development of components that might replace silicon chips in current computers," he added. This research can also determine the chemical properties of nanosystems, which could lead to 'greener' technology. McGill University cited as an example using nanoparticles to improve the energy efficiency of lighting systems.

University of Washington: Fall Lecture Series


Each fall, the UW College of Engineering partners with the UW Alumni Association to present a series of free lectures featuring their distinguished faculty and industry experts. The 2009 lectures are being broadcast on UWTV and are available on-demand.

Intel's silicon future


In this video Paul Otellini lays out the current state of Intel's silicon operations to shareholders at the company's annual Investor Day in Santa Clara.

Google Buzz a Spammer Bonanza?


Scientists show how the social network could be mined for e-mail addresses.Users who are still displaying their Google Buzz following / follower list on their Google profiles are leaving themselves open to spammers and, potentially, sophisticated phishing attacks.

Ways to improve your Interview Skills


With so much useful advise and talented career experts out there with often differing opinions, you will most likely end up in a 'black hole' wasting your precious time and money in the process. This blog was created when i was interviewing way back in 2004 mainly as a placeholder for collecting all the interview questions i faced and documenting all the stupidities, oddities and irrelevance i had to go through in that process. More so often i had to come across so many head hunters and career search firms who failed to pay attention to the detail or not experienced enough to understand the requirements of the candidate or the job. The outcome is once wasted interview opportunity and the likelihood that you may not interview with that firm again. But all these facts should not demotivate you as this world is full of surprises and be ready to take on hurdles as they come along.With that in mind, I promise if you take some 30 odd minutes to read these posts, you'll already be ahead of the game. Apply some of the techniques, and I guarantee you'll see some results.
Best of luck.

Challenges of a Fabless Semiconductor Startup Company in Consumer Electronics


Consumer electronics remains one of the fastest growing business markets in today's world and provides many opportunities for technical growth. What do you think are the Technical and Business Challenges of a Fabless Semiconductor Startup Company in Consumer Electronics.

Researchers Create Logic Circuits From DNA


Researchers at Duke University recently used DNA to craft tiny chips used in computers and electronic circuits. By mixing DNA snippets with other molecules and exposing them to light, researchers created self-assembling, DNA-based logic circuits. Once perfected the tech could serve as an endlessly abundant, cheap alternative to silicon semiconductors. Chris Dwyer, lead researcher on the project, says that one grad student using DNA to make self-assembling circuits could produce more logic circuits in one day than the global silicon chip industry can create in an entire month!"

Win great prizes by answering the Interview Questions**


One of the most popular topics on this blog is the series on Interview Questions. With over 105 Interview Questions, many of which are original and unique we continue in that trend to post a new set very often. It just does not stop here. The person who can answer all questions right in the comments sections, stands a chance to win a Home Burglar Alarm with integrated motion sensor, 105db loud buzzer, Wall-mount and remote activation. (** The person needs to answer all questions correctly in a given set starting with the questions posted from May 2010. The product will only be shipped for free to addressee in India. Shipping charges of $10 applies for addressees outside India. Last but not the least, you have to support this blog by first registering as a follower in the Join this Blog section (google sign-up), be part of the Facebook fan page and should be subscribed to our rss feeds or email!).

Wilder Technologies Launches Line of Test Adaptor Products for Test & Measurement Companies


Vancouver, WA -- Wilder Technologies has released a new family of test adaptor products for the test & measurement industry that allow users to test and validate their designs for compliancy based on individual high speed serial protocol standards and to assist in finding out deficiencies in their products. Designed to deliver the highest electrical performance, Wilder’s products are used by design engineers, test and measurement engineers, validation engineers and compliance test engineers to detect defects through the use of the test fixtures and establish the failure criteria accurately.

Priced in the $2-3K range, Wilder’s products have demonstrated effectiveness via outstanding S-Parameters, TDR measurements, 3D EM models to empirical measurements for true design accuracy. The test adaptors work with test and measurement companies in mechanical, electrical and signal integrity design.

“Our team has worked together in test and measurement companies with a combined experience of over 125 years in mechanical, electrical and Signal Integrity design, including extensive experience in field engineering, manufacturing, applications and customer support,” explained Wilder Technologies founder Paul Deringer.

Using a systemic approach to solve signal integrity challenges via high-speed, high-performance Test Adapters, Wilder has initially released several test adaptor products including Display Ports, SATA, SAS and HDMI .

Located in Vancouver, WA, Wilder Technologies is committed to solving signal integrity challenges using time and frequency domain analysis, measurement techniques, and state of the art tools and design methodologies to develop metrological solutions for a broad range of companies in the telecommunications and other industries.

For more information, visit www.wildertechnologies.com.

Cambridge Wireless is Unlocking New Semiconductor Opportunities in Connectivity 20th May 2010, Cambridge, UK


Cambridge Wireless has announced the second meeting of the popular semiconductor Special Interest Group meeting taking place on 20th May in Cambridge where it is hosted by the Bluetooth giant company, CSR. For more information, please visit www.cambridgewireless.co.uk/events

This discussion will examine current and future developments in semiconductors that will provide the data throughput required for new applications, and also the semiconductor devices that will support these applications on battery-powered mobile devices.
Peter Claydon of Silicon Southwest, who is a champion of this SIG comments, “for this event we’ve gathered together an impressive set of speakers from many of the world’s most forward-thinking chip companies. I’m looking forward to some lively and informed debate on developments that will shape all our futures over the next ten years”.

The ability of networks to deliver high data throughput to users is in part governed by the development of more sophisticated modulation techniques and algorithms, but the ability to deploy these in the real world is wholly dependent on developments in the semiconductor arena that enable the implementation of these algorithms for an acceptable cost and power consumption. This applies both to terminal devices, which may be handsets, data cards, powerline adaptors or increasingly embedded in other devices, such as the Amazon Kindle, and to network devices that enable smaller and cheaper base stations, including femtocells and backhaul solutions.

It is a truism that the development of applications follows the availability of the underlying networks that support the required data throughput. For example, YouTube and Spotify would not be possible without widespread availability of wired broadband. So what are the applications that are driving the need for higher data throughputs and what semiconductor devices are being developed that will support these applications?

Attendees will hear from and debate with the following industry specialists:
• Raj Gawera, Vice President of HBU Marketing at CSR
• Mike Muller, CTO at ARM
• Gordon Lindsay, Associate Director at Broadcom Europe
• Ben Timmons, Senior Director of Business Development at Qualcomm
• Tim Fowler, Commercial Director at Cambridge Consultants

“This event highlights the ever changing demands faced by the semiconductor industry being driven by the need for efficient movement of higher and higher levels of data within acceptable levels of power consumption,” explained Eric Schorn, VP of Marketing, Processor Division, ARM. “ARM is investing to address these challenges and is a great supporter of innovation in this field which will enable us to help deliver the wired and handheld devices of tomorrow.”

This SIG is championed by Eric Schorn of ARM, Peter Claydon of Silicon Southwest and Carson Bradbury of Cre8Ventures.

Access Wireless Sensor Networks from portable computing devices


Libelium, a technology leader in distributed wireless networks, announced a new Bluetooth module for its Waspmote wireless sensor network (WSN) platform. This module enables wireless sensor networks to be directly linked to portable devices such as smart phones, PDAs and laptop computers. This capability is particularly useful for medical applications and for industrial diagnostics. Additionally, when combined with the Meshlium multi-protocol router, it supports the deployment of hybrid ZigBee- and Bluetooth-based wireless sensor networks.

The new Bluetooth module extends the Waspmote platform by offering a new choice for radio communication. The platform is extremely modular allowing the use of a wide range of modules for both wireless communication and sensors. Now WSN users can choose between a Bluetooth module and a range of ZigBee modules covering the main frequency bands (2.4GHz, 868MHz, 900MHz). Libelium CTO David Gascón says, “This module will be particularly useful for medical applications requiring the integration of biometric sensors and for sending sensor information to Bluetooth-equipped industrial systems”. He adds, “Users with existing Bluetooth-based infrastructure will be able to extend it to include Waspmote and its range of sensors”.

The new module exploits key features of the platform such as power management. The Waspmote internal microprocessor minimises energy consumption by switching the radio module on and off at the necessary intervals. The new module is able to send sensor data frames to smart phones that support Serial Port Profile. Security mode is implemented with PIN validation which can be preconfigured such as a “Network Key” and it allows the management of a Trusted Nodes list in order to create secured networks.

Waspmote users are also now able to build hybrid networks with both Bluetooth and ZigBee sub-networks if they use the Libelium Meshlium multi-protocol router to bridge between the sub-networks. With both Bluetooth and ZigBee using the 2.4GHz industrial, scientific and medical (ISM) radio band there is the possibility of interference. For this reason Waspmote enables Bluetooth and ZigBee communication to work in the same environment by using Adaptive Frequency Hopping (AFH) which enables the Bluetooth radio to dynamically identify channels already in use and to avoid them.

Users are able to flexibly change a device between ZigBee and Bluetooth as all the modules use the same kind of socket on the Waspmote board. The platform has an open source API and programming environment; new libraries are available to support the Bluetooth module. David Gascón says “Waspmote’s architecture means that each additional module adds value to the platform”. Complete documentation and code examples can be found at http://www.libelium.com/waspmote.

Libelium is exhibiting at Sensor+Test ("17th International Trade Fair for Sensorics, Measuring and Testing Technologies") from 18th-20th May 2010 in Nuremberg, Germany. The Waspmote and Meshlium products will be demonstrated in Hall 12, stand 12-227.

Every day at 13:30-13:45, Libelium will show the wireless sensor network Waspmote platform in the Action Area.

On Thursday 20th May at 9:30-10:00, Libelium CTO, David Gascón, will present “Waspmote, a Sensor Device Platform for developing Wireless Sensor Networks (WSN)” as part of Programme Hall 12.

More information: http://www.libelium.com/waspmote

About Wireless Sensor Networks
Wireless sensor networks (WSN) consist of small battery powered electronic devices – often known as “motes” – which gather data from built-in sensors. A WSN is self-organising allowing it to have high availability, scalability and simple installation. Applications include environmental monitoring, fire or gas detection, smart metering, farming, logistics and security.

For more information visit http://www.libelium.com/products/waspmote/wsn

About Waspmote
Waspmote is a modular platform for building wireless sensor networks. The platform comprises:
the Waspmote board with microcontroller, memory, battery, accelerometer and sockets for add-on modules; open source API and compiler; Xbee range of ZigBee wireless communication modules offer a choice of protocol versions, radio frequency and range (up to 40 km); wireless modules supporting Bluetooth, GPRS, GPS; a gas sensor board supports the detection of gases arising from industrial pollution, fires, farms and chemical and industrial processes; a physical event detector board support security, flood detection and vibration and impact monitoring; and outstanding power management - an unprecedented 0.7 microamperes is required in hibernate mode.
Waspmote is CE, FCC and IC certified.

For Waspmote platform details visit http://www.libelium.com/waspmote

About Libelium
Libelium designs and manufactures hardware and communication protocols for distributed wireless networks. The product portfolio consists of the Waspmote low power platform for creating wireless sensor networks; the Meshlium multi-tech router integrating WiFi mesh (2.4GHz - 5GHz), ZigBee, GPRS, GPS and Bluetooth technologies; and N-vio platform for proximity marketing and messaging via Bluetooth.

The company was founded in 2006, is privately held and is based at the European Business and Innovation Centre CEEIARAGON, Zaragoza, Spain.

For more information call +34 976 54 74 92 or visit http://www.libelium.com

VSIDE - VSDSP Integrated Development Environment


VLSI Solution has announced VSIDE - the Integrated Development Environment for VSDSP Processor Family. VSIDE is an integrated development environment for VLSI Solution's 16/40-bit VSDSP digital signal processor family. It contains a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, profiler, etc. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows XP or Vista platform.

VSIDE supports emulator-based debugging using real hardware. It also contains several example projects to help users get easily started. The beta version of the tool has been successfully used in the development of many audio products such as echo cancellation for Skype phone and pitch shifting of the audio source for a portable karaoke product. DSPeaker's (www.dspeaker.com) award winning Anti-Mode™ algorithm was debugged in a short time by using the powerful tools of VSIDE.

VSIDE currently supports VLSI Solution's audio codec chip VS1053 as well as VLSI's all-new digital signal processor circuit VS8053. Support for the low cost VS1000 audio system chip will be added by Q1/2011. VLSI Solution's current programming examples will gradually be ported to VSIDE.

Keeping with the spirit of VLSI Solution's openness policy, VSIDE can be downloaded for free at: http://www.vlsi.fi/en/support/software/vside.html

About VLSI Solution
VLSI Solution is an innovative new technology creator that designs and manufactures integrated circuits. Within its 19 years of existence VLSI has build an extensive in-house IP library and has the capability to pull through complicated mixed-signal IC projects, ranging from digital audio to RF applications.

For more information, see http://www.vlsi.fi/

VLSI/ASIC/VHDL Interview Questions


One of the most popular topics on this blog is the series on Interview Questions. With over 105 Interview Questions, many of which are original and unique we continue in that trend to post a new set today. It just does not stop here. The person who can answer all questions right in the comments sections, stands a chance to win a Home Burglar Alarm device with integrated motion sensor** (Details will be posted later and the product will only shipped to addressee in India).

Now for the Questions!
1. For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the process. Please give a detailed reason and an exception to this statement.
2. For a combinational process, every signal that is assigned to, must be assigned to in every branch of If-Then-Else statement and Case statement. Why?
3. Each signal should be assigned to in only one process. Please give a detailed reason and an exception to this statement.
4. Separate unrelated signals into different processes. Give atleast two reasons!
5. In a state-machine, illegal and unreachable states should transition to the reset state. Explain.
6. If your state-machine has less than 16 states, use a one-hot encoding. Explain.
7. Include a reset signal in all clocked circuits. Explain.
8. For implicit state-machines, check for reset after every wait statement.
9. Connect reset to the important control signals in the design, such as the state signal. Do-not reset every flip-flop. Explain.
10.Use synchronous, not asynchronous reset. Explain.

**Only original answers will be eligible for the lucky draw. Google searched and copied answers will be disqualified.
Last but not the least, you have to support this blog by first being a follower in the Join this Blog section (google sign-up), part of the Facebook fan page and should be subscribed to rss feeds!
Good luck.

Information


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For advertising options and queries you can contact us at the same address.

Press Release: Baolab creates nanoscale MEMS inside the CMOS wafer


Baolab Microsystems has announced a new technology to construct nanoscale MEMS (Micro Electro Mechanical Systems) within the structure of the actual CMOS wafer itself using standard, high volume CMOS lines, which is much easier and quicker with fewer process steps than existing MEMS fabrication techniques that build the MEMS on the surface of the wafer. This significantly reduces the costs of a MEMS by up to two thirds and even more if several different MEMS are created together on the same chip.

The Baolab NanoEMS™ technology uses the existing metal layers in a CMOS wafer to form the MEMS structure using standard mask techniques. The Inter Metal Dielectric (IMD) is then etched away through the pad openings in the passivation layer using vHF (vapour HF). The etching uses equipment that is already available for volume production and takes less than an hour, which is insignificant compared to the overall production time. The holes are then sealed and the chip packaged as required. As only standard CMOS processes are used, NanoEMS MEMS can be directly integrated with active circuitry as required.

"We have solved the challenge of building MEMS in a completely different way," explained Dave Doyle, Baolab's CEO. "Existing MEMS technologies are slow, expensive and require specialist equipment. They have to be either built on top of the wafer at a post production stage or into a recess in the wafer. By contrast, our new NanoEMS technology enables MEMS to be built using standard CMOS technologies during the normal flow of the CMOS lines."

Baolab has successfully created MEMS devices using standard 0.18um 8" volume CMOS wafers with four or more metal layers, and has achieved minimum feature sizes down to 200 nanometres. This is an order of magnitude smaller than is currently possible with conventional MEMS devices, bringing the new NanoEMS MEMS into the realm of nanostructures, with the additional benefits of smaller sizes, lower power consumption and faster devices.

Baolab will be making a range of discrete MEMS including RF switches, electronic compasses and accelerometers, along with solutions that combine several functions in one chip. The prototype stage has already proved the NanoEMS technology and evaluation samples will be available later this year. These are aimed at handset designers and manufacturers, and Power Amplifier and RF Front End Module markets.

For further information on Baolab Microsystems, please go to www.baolab.com.
e-mail: info[at]baolab[dot]com
Institut Politècnic del Campus de Terrassa, 08220 Terrassa, Spain.
Tel.: +34-93-394-17-70

Press contact for interviews and illustrations is Nigel Robson, Vortex PR.
e-mail: Nigel[at]vortexpr[dot]com
Tel: +44 1481 233080
NanoEMS is a trademark of Baolab Microsystems, S.L.

Grid Computing Vs Cluster Computing


A cluster computer is a set of CPU nodes that are used to solve any problem over a network. The way in which this cooperation is accomplished among the computers to solve a problem is called Cluster Computing. In Grid computing, the idea is very similar to Cluster Computing however they are used for solving large problems. Clusters are usually homogeneous and Grids are heterogeneous. Homogeneous is where all CPU nodes have the same Hardware configuration and OS. A cluster of clusters is usually a Grid. CPU nodes that are part of a Grid need not be homogeneous and are usually spread across LANs or WANs.

Words of wisdom


Flattening of the Design Hierarchy – Components are tied with architectures. Also produces a large number of processes representing each low-level component that communicate via nets (signals).