Intelligent 4G basestations to be powered by Intel


The Inquirer reports that Ubiquisys has announced that it will develop WiFi base stations using Intel's processors. The intelligent base stations that Ubiquisys is developing are small cells for use in public spaces and big businesses. The need for Intel's processor comes from the growing need to have content within the principality of the base station rather than pulling everything off the internet.

EEWeb Site of the day - May 25, 2011


We are listed on EEWeb Site of the day - May 25, 2011. EEWeb is a premier electrical engineering community that strives to offer its members the best online resources for hardware designers. EEWeb is independently owned and operated by co-founders Cody Miller and Joe Wolin. The development of the site began in late 2007 and was released in late 2010. We have partnered with Digi-Key Corporation as an exclusive sponsor of EEWeb and we are proud to promote Digi-Key's first-class products and services.

Cyclic Redundancy Checking (CRC) - Part 3


Augmentation is a technique used to produce a null CRC result, while preserving both the original data and the CRC checksum. In communication systems using cyclic redundancy checking, it would be desirable to obtain a null CRC result for each transmission, as the simplified verification will help to speed up the data handling.

Traditionally, a null CRC result is generated by adding the cyclic redundancy
checksum to the data, and calculating the CRC on the new data. While this
simplifies the verification, it has the unfortunate side effect of changing the data. Any node receiving the data+CRC result will be able to verify that no corruption has occurred, but will be unable to extract the original data, because the checksum is not known. This can be overcome by transmitting the checksum
along with the modified data, but any data-handling advantage gained in the verification process is offset by the additional steps needed to recover the original data.

Augmentation allows the data to be transmitted along with its checksum, and still obtain a null CRC result. As explained before when obtain a null CRC result, the data changes, when the checksum is added. Augmentation avoids this by shifting the data left or augmenting it with a number of zeros, equivalent to the degree of the generator polynomial. When the CRC result for the shifted data is
added, both the original data and the checksum are preserved.

In this example, our generator polynomial (x3 + x2 + 1 or 1101) is of degree 3, so the data (0xD6B5) is shifted to the left by three places or augmented by three zeros.
0xD6B5 = 1101011010110101 becomes 0x6B5A8 = 1101011010110101000.

Note that the original data is still present within the augmented data.
0x6B5A8 = 1101011010110101000
Data = D6B5 Augmentation = 000
Calculating the CRC result for the augmented data (0x6B5A8) using our generator polynomial (1101), gives a remainder of 101 (degree 2). If we add this to the augmented data, we get:
0x6B5A8 + 0b101 = 1101011010110101000 + 101
= 1101011010110101101
= 0x6B5AD

As discussed before, calculating the cyclic redundancy checksum for 0x6B5AD will result in a null checksum, simplifying the verification. What is less apparent is that the original data is still preserved intact.

0x6B5AD = 1101011010110101101
Data = D6B5 CRC = 101

The degree of the remainder or cyclic redundancy checksum is always less than the degree of the generator polynomial. By augmenting the data with a number of zeros equivalent to the degree of the generator polynomial, we ensure that the addition of the checksum does not affect the augmented data.

In any communications system using cyclic redundancy checking, the same generator polynomial will be used by both transmitting and receiving nodes to generate checksums and verify data. As the receiving node knows the degree of the generator polynomial, it is a simple task for it to verify the transmission by calculating the checksum and testing for zero, and then extract the data by discarding the last three bits.

Thus augmentation preserves the data, while allowing a null cyclic redundancy checksum for faster verification and data handling.

Will Intel's 3D transistor fuel a tablet fight with ARM?


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Developing Silicon IP with Open Source Tools


The electronic design automation (EDA) tool industry is big business, and commercial licenses are extremely expensive. Open standards have driven many proprietary EDA technologies to be publicly released as free/libre open source software (F/LOSS) and some have become IEEE standards. In this article, author Arthur Low reviews the history of key advances in ICs and EDA tools. The common theme presented in this article for the driver of technology innovation is the requirement to develop the most advanced microprocessor possible. Today, a low-cost, high-value-added business model can efficiently serve the market for IC subsystems licensed as intellectual property (silicon IP) in the form of compilable source code. Alternatively, for larger SoC designs, engineering budgets can be shifted from the purchase of a relatively small number of high-cost EDA tool licenses to open source EDA technologies that can be run on massive compute-server farms. The two business models are not theoretical, but realistic. The author explains how his company (Crack Semiconductor) developed commercially successful cryptographic silicon IP using entirely open source EDA technologies and how another company (SiCortex) pushed the limits of IC design and open source EDA tools by simulating and verifying a massively parallel supercomputer.