World's first Carbon Nanotube based Computer


A Carbon Nanotube with its unique properties are a big breakthrough for electronics. Due to their thermal conductivity, mechanical and electrical properties, they find applications as additives to various structural materials. A team of Stanford engineers have taken this and built a basic computer harnessing the huge energy conservation capabilities and thereby promising to extend 'Moore's Law' for years to come.

Intel co-founder Gordon Moore's 1965 prediction that computer circuitry will keep getting smaller and cheaper to produce has held up. But as integrated circuits (ICs) keep getting more densely populated with transistors, the large amounts of heat they dissipate have prompted concerns over whether silicon can be used for many more generations of transistor shrinkage.



"People have been talking about a new era of carbon nanotube electronics moving beyond silicon. But there have been few demonstrations of complete digital systems using this exciting technology. Here is the proof," Mitra said in a statement.






Mihail Roco, senior advisor for Nanotechnology at the National Science Foundation, called the Stanford work "an important, scientific breakthrough". The research was led by Stanford professors Subhasish Mitra and H.S. Philip Wong.

Non-Synthesizable VHDL Code


RTL Synthesis is done by matching high level code against templates or patterns. It is important to use idioms that your synthesis tool recognizes. If you aren’t careful, you could write code that has the same behavior as one of the idioms, but which results in inefficient or incorrect hardware.





Most synthesis tools agree on a large set of idioms, and will reliably generate hardware for these idioms. This post is based on the idioms that Synopsys, Xilinx, Altera, and Mentor Graphics are all able to synthesize. We consider combinational loops to be unsynthesizable. Although it is obviously possible to build a circuit with a combinational loop, in most cases the behaviour of such a circuit is undefined.

Initial Values
Initial values on signals (UNSYNTHESIZABLE)
signal bad_signal : std_logic := ’0’;
Reason: In most implementation technologies, when a circuit powers up, the values on signals are completely random. Some FPGAs are an exception to this. For some FPGAs, when a chip is powered up, all flip flops will be ’0’. For other FPGAs, the initial values can be programmed.

Wait For
Wait for length of time (UNSYNTHESIZABLE)
wait for 10 ns;
Reason: Delays through circuits are dependent upon both the circuit and its operating environment, particularly supply voltage and temperature.

Different Wait Conditions
wait statements with different conditions in a process (UNSYNTHESIZABLE)
-- different clock signals
process
begin
wait until rising_edge(clk1);
x <= a;
wait until rising_edge(clk2);
x <= a;
end process; 

-- different clock edges
process
begin
wait until rising_edge(clk);
x <= a;
wait until falling_edge(clk);
x <= a;
end process; 

Reason: Processes with multiple wait statements are turned into finite state machines. The wait statements denote transitions between states. The target signals in the process are outputs of flip flops. Using different wait conditions would require the flip flops to use different clock signals at different times. Multiple clock signals for a single flip flop would be difficult to synthesize, inefficient to build, and fragile to operate.

Multiple “if rising edge”s in Same Process
Multiple if rising edge statements in a process (UNSYNTHESIZABLE)
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
end if;
if rising_edge(clk) then
q1 <= d1;
end if;
end process;
Reason: The idioms for synthesis tools generally expect just a single if rising edge statement in each process. The simpler the VHDL code is, the easier it is to synthesize hardware. Programmers of synthesis tools make idiomatic restrictions to make their jobs simpler.

“if rising edge” and “wait” in Same Process
An if rising edge statement and a wait statement in the same process (UNSYNTHESIZABLE)
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
end if;
wait until rising_edge(clk);
q0 <= d1;
end process;
Reason: The idioms for synthesis tools generally expect just a single type of flop-generating statement
in each process.

“if rising edge” with “else” Clause
The if statement has a rising edge condition and an else clause (UNSYNTHESIZABLE).
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
else
q0 <= d1;
end if;
end process;
Reason: Generally, an if-then-else statement synthesizes to a multiplexer. The condition that is tested in the if-then-else becomes the select signal for the multiplexer. In an if rising edge with else, the select signal would need to detect a rising edge on clk, which isn’t feasible to synthesize.

“if rising edge” Inside a “for” Loop
An if rising edge statement in a for-loop (UNSYNTHESIZABLE-Synopsys)
process (clk) begin
for i in 0 to 7 loop
if rising_edge(clk) then
q(i) <= d;
end if;
end loop;
end process;
Reason: just an idiom of the synthesis tool.
Some loop statements are synthesizable. For-loops in general are described in the VHDL cookbook by Ashenden. For the curious reader, the above code is an 8-bit serial-to-parallel converter. The signal d is the serial data and q is the parallel data. On each clock cycle, d is copied into one of the bits of q.

For the synthesizable alternatives, please discuss/leave comments below.

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Links & Resources (Link your website/blog)


This is an archive of the Links and Resources from the electronics web community submitted here so far. Please add your own link using the form below, but be advised that non related (spam) links will not be entertained.






A................................................................................................................
ASIC-System On Chip (SoC)-VLSI Design
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C................................................................................................................
CAD 4 VLSI
CAD and VLSI
Chip Design Made Easy
Coaching Excellence in IC Design Teams
Computer Harware links
Consciousness as the theory of everything
Cool Verification
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D................................................................................................................
Daniel Nenni
DeepChip
Design For Testability Blog
DFT Digest
Digital IC Design
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e Verification
EET Design
EET Semi
EEWeb Electronics Forum - Electrical Engineering Community
Embedded System Design
Eric Schorn's Processors for People Blog
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Fahrvergnugen
FPGA and DSP from scratch
FPGA Computing
Future of Design
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Hardware Description and Verification Language
harry ... the ASIC guy
hdlsnippets - Releveant and accurate HDL snippets in verilog, system verilog and VHDL.
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Industry Insights
IntelligentDV -Blog
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John Cooley's DeepChip.com
John's Semi-Blog
JTAG
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Kiran Bulusu's Blog
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Linley Chips In
Listening Post
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Magic Blue Smoke
My Electronics Blog
..
N................................................................................................................
Nadav's Tech Adventures
Nanotech
Ninja ASIC Verification
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O................................................................................................................
Oh, one more thing
Olivier Coudert's Blog
On Verification: A Software-to-Silicon Verification
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Pallab's Place
Practical Chip Design
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Reconfigurable Computing
RocketBlog - a discussion about all things related...
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S................................................................................................................
Semiconductor Glossary BLOG
skmurphy
Specman Verification
Studying and practicing Electronics
SysWip- For free open source SystemVerilog verification IPs.
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T................................................................................................................
Taking the Measure
Tao of ASICs
TestBench
The Eyes Have It
The Inquirer
The Solar Cell Corner
The Standards Game
The Tao Of ASICs
The Ultimate Hitchhiker's Guide to SV- VMM
The Xuropean
Think Verification - Tips Insights on ASIC Verification
Tips for HVL and HDL users with special emphasis on...
Travelling On The Silicon Road
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V................................................................................................................
Verification Martial Arts
Verification Vertigo
VerificationOnWeb (VoW)
verifyurdesign
VeriGood
Verilab
Verilab Blog
VHDL Guru - Coding, Tips & Tricks (New)
VLSI core
VLSI FAQ
VLSI int Q's from Google
VLSI Interview Questions
VLSI The Chip Insider
VLSI, VLSI CAD, and Programming WareHouse
VLSIhomepage
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