tag:blogger.com,1999:blog-10948316.post9102944520681410388..comments2024-11-03T20:11:25.698+05:30Comments on The Digital Electronics Blog: NVIDIA Interview QuestionsThe Administratorhttp://www.blogger.com/profile/16559655046456902358noreply@blogger.comBlogger6125tag:blogger.com,1999:blog-10948316.post-8571684389233593622012-10-17T01:46:50.785+05:302012-10-17T01:46:50.785+05:309) False. Redundancy in a sub-circuit means that t...9) False. Redundancy in a sub-circuit means that there exists an undetectable fault (ex: stuck-at faults) in that sub-circuit. This does not mean it masks ALL of the other faults! moaxgeninoreply@blogger.comtag:blogger.com,1999:blog-10948316.post-28728636267793220552012-10-17T01:41:23.361+05:302012-10-17T01:41:23.361+05:308) Yes, basic concept is true. You will find that ...8) Yes, basic concept is true. You will find that for an N-bit binary counter, For the 1st bit, N bits toggle, then for the 2nd bit, N/2 bits toggle, then for the 3rd bit, N/4 bits toggle. So calculating the total number of toggles (switches), we see a total of N+N/2+N/4+N/8+... toggles, which converges to 2*N toggles for a normal binary counter. For a gray counter, for N bits, since every count we only change 1 bit, we have N toggles total for each min to max count. So for a 32-bit state, which translates to 5 bits, we can have 50% lower power consumption in dynamic switching power from just using a gray counter. HOWEVER, one must remember that at very low power levels, leakage power becomes exponential - so there's a level of whether you really care that much about implementing gray coding using up valuable real estate space on your chip layout to do this.moaxgeninoreply@blogger.comtag:blogger.com,1999:blog-10948316.post-19063678878307536812011-01-18T08:09:08.496+05:302011-01-18T08:09:08.496+05:30Hi
I like this post:
You create good material ...Hi<br /><br />I like this post: <br /><br />You create good material for community.<br /><br />Please keep posting.<br /><br />Let me introduce other material that may be good for net community.<br /><br />Source: <a href="http://manufacturinginterviewquestions.blogspot.com/" rel="nofollow">Manufacturing interview questions</a><br /><br />Best rgs<br />PeterAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-10948316.post-57889356304355263482009-08-09T20:17:42.777+05:302009-08-09T20:17:42.777+05:303) this is justification for statement 3:
to check...3) this is justification for statement 3:<br />to check if a 16 bit number is some constant requires a 16 input AND gate.<br /><br />theoretically, if one views "P=656" as selecting one entry in the truth table formed all combinations (2^16) input P, then P=656 => P9&P7&P4&(all other bit positions zero). this follows from the binary representation of 656. a 16 input AND can be created with 4 LUTs for 1st stage compression and one more LUT for final compression. So, 5 LUTs are requiredAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-10948316.post-44015348853869780682008-11-15T05:42:00.000+05:302008-11-15T05:42:00.000+05:30I am not sure about all the answers but trying to ...I am not sure about all the answers but trying to answer some of them. Please verify somewhere else too.<BR/>2) No. Asynchronous resets are used in the designs too. However synchronous reset is normally adopted.<BR/>6) Yes. Before the chip has been taped out, if there is a hold violation, the addition of buffers should resolve them.<BR/>7) Voltage scaling is scaling down the supply voltages with an intention of reducing the power dissipation. Other parameters do get affected by it. For eg: Threshold voltage and delay.<BR/>9) Well, it is not necessarily true. the redundant logic can also be tested for faults.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-10948316.post-71315981287553327452008-07-22T11:30:00.000+05:302008-07-22T11:30:00.000+05:30Hi,Please can you post the answers to the question...Hi,<BR/>Please can you post the answers to the questions in detail.<BR/>thank youAnonymousnoreply@blogger.com