Verilog and Specman 'e' Interview Questions
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
A communication device receives a clock up to X MHz. Write a verilog to verify that the clock meets this timing require…
Consider the Boolean function F = ( x1 + x3 + x4 )(x2 + x3 + x4 )(x1 + x2 +x4)(x1 +x3 +x4)( x1 +x2 + x3 ). Find an…
Packets dispatched can be of 3 network types: atm, ieee or Ethernet. The packets have a Boolean flag field which indica…
A CPU has a memory unit with 32-bit instructions and a register file with 32 registers. The instruction set consists of…
Draw the circuit diagram for barrel-shifter that can shift 3 bits in either direction. The shifter should take 3 bits a…
It has been a while since we posted any puzzles or interview questions to tickle everyone's teeny brains. Recession…
In Verilog and VHDL, there are three types of delays that are commonly used in digital logic simulation: delta delay,…
How do you minimize clock skew/ balance clock tree? Given 11 minterms and asked to derive the logic function. Given C…
How do you optimize power at various stages in the physical design flow? Power optimization is an important aspect of p…
What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations? Explai…
RTL Design In work Design Verification In work Physical Design In building the timing constraints, do you need to const…
How are timing constraints developed? Explain timing closure flow/methodology/issues/fixes. Explain SDF (Standard Del…
What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)? What was the a…
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Hello Readers, Due to the recent spate of Layoffs , a high amount of panic and interview preparation frenzy has seeped…
One day you are strolling the hallways in search of inspiration, when you bump into a person from the marketing departm…
Your task is to do the power analysis for a circuit that should send out a one-clock-cycle pulse once every 16 clock cy…
Your manager has given you the task of implementing the following pseudo code in an FPGA: if is_odd(a + d) { p = (a +…
This is a famous interview question just that it has got a makeover! Question: Construct a "divisible-by-3"…