Showing posts with label Transport delay / Inertial Delay. Show all posts
Showing posts with label Transport delay / Inertial Delay. Show all posts

Transport delay / Inertial Delay


A number of types of delays exist for describing circuit behavior. The two major hardware description languages, Verilog and VHDL, support inertial delay and transport delay.
Inertial delay is a measure of the elapsed time during which a signal must persist at an input of a device in order for a change to appear at an output. A pulse of duration less than the inertial delay does not contain enough energy to cause the device to switch. This is illustrated in Figure attached where the original waveform contains a short pulse that does not show up at the output.






Transport delay is meaningful with respect to devices that are modeled as ideal conductors; that is, they may be modeled as having no resistance. In that case the waveform at the output is delayed but otherwise matches the waveform at the input. Transport delay can also be useful when modeling behavioral elements where the delay from input to output is of interest, but there is no visibility into the behavior of delays internal to the device.