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Flattening of the Design Hierarchy – Components are tied with architectures. Also produces a large number of processes representing each low-level component that communicate via nets (signals).
The analysis of critical paths and false paths assumes that all inputs change values at exactly the same time. Timing differences between inputs are modelled by the skew parameter in timing analysis.
To exercise a path, only one inputs needs to change. Stated another way, if a path cannot be exercised by toggling one input, then the path cannot be exercised by toggling more than one input.
Cycle Simulation – This technique computes the steady state response of the circuit at each clock cycle boundary, not taking into account detailed circuit timing. No concept of delta cycle.
Elaboration of Declarations - Type consistency, etc done through following the rules that govern the declaration and initialization of signals and variables.
Simulation cycle is the simulator step time i.e. a time value at which the clock in the design is being run like 10 ns, 200 ns, etc
Simulation – Involves execution of the user-defined processes that interact with each other and with the environment. This is done through event generation based on simulation time, and causing the appropriate effected processes to respond to those events. Synopsys/Scirocco uses 'scsim' and Xilinx/Modelsim uses 'vsim' as their simulation engine.
Elaboration – Involves flattening the hierarchical description of the design to produce a netlist of processes. Signals and variables are initialized. The resulting model is ready to be simulated. Synopsys/Scirocco uses 'scs' and Xilinx/Modelsim uses 'vcom' for elaboration.
Delta cycles are used by the simulator to order events within a simulation cycle. A delta cycle has an infinitesimally small delay and it does not appear on the trace waveform produced for analysis.
To extend your phones battery life: All things being equal, the C.D.M.A. mobile standard uses more power than a G.S.M. network. If battery life is critical, you might want to consider G.S.M. as long as its coverage meets your needs.
Inertial Delay – Default delay type in VHDL. Used to model gates that do not propagate short pulses. Any signal with a pulse-width shorter than the specified delay time is rejected.
Transport Delay – Intended to model wiring delay. Simply delays the signal by specified delay time.
If a signal is updated with the same value it had in the previous simulation cycle, then it does not change, and therefore does not trigger processes to resume.
Combinational for-loops are usually synthesizable. They are often used to build a combinatorial circuit for each element of an array.
Clocked for-loops are not synthesizable, but are very useful in simulation, particularly to generate test vectors for test benches.
Spend the time up front to plan a good design on paper. Use dataflow diagrams and state machines to predict performance and area. Usually a block might appear to be sufficiently small and simple that you can go straight to RTL code. However, you will probably produce a more optimal design with less effort if you explore high-level optimizations with dataflow diagrams and state machines.
The phrases "behavioural model" and "structural model" are commonly used for "high-level models" and "synthesizable models". In most cases, what people call structural code contains both structural and behavioural code. The technically correct definition of a structural model is an HDL program that contains only component instantiations and generate statements.
Analysis – Synonymous with compiling VHDL programs. Analyzer performs the customary syntactical checks, code generation, compilation and places the resulting model in the default design library WORK. Synopsys/Scirocco uses 'vhdlan' for analysis and Xilinx/Modelsim uses 'vcom'
Transaction – It occurs on a signal when a new assignment has been made to the signal, but the value may not have changed. It is a time-value pair where the value represents a future value of the signal and time represents when the update happen.
Postponed in VHDL terminology is a synonym for some operating systems usage of ready, to describe a process that is ready to execute.