ARP
ARP Q&A
What is ARP? Address Resolution Protocol (ARP) is a network protocol, which maps a network layer protocol address to a …
Ethernet
Ethernet Q&A
What is Ethernet? Ethernet is a Local Area Network (LAN) cabling and signaling specification for baseband networks. Eth…
Algorithms
Algorithms and High-Level Models
For designs with significant control flow, algorithms can be described in software languages, flowcharts, abstract stat…
Coding
“behavioural model” & “structural model”
The phrases "behavioural model" and "structural model" are commonly used for what we'll call &q…
Design
Basic aspects of a typical digital design flow...
Requirements Description of what the customer wants Algorithm Functional description of computation. Probably not synth…
Guidelines
General FPGA based design Guidelines
Based on past experience i had with FPGAs... Flip-flops are almost free in FPGAs, the reason is that in FPGAs, the area…
Synchronization
Asynchronous in a synchronous world - Part 2
Performing static timing analysis is the process of verifying that every signal path in a design meets required clock-c…
Synchronization
Asynchronous in a synchronous world - Part 1
The purpose of synchronizing signals is to protect downstream logic from the metastable state of the first flip-flop in…
Synchronization
Asynchronous in a synchronous world - Introduction
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article…
Coding
Verilog code to detect if a 64bit pattern can be expressed using power of 2
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + dat…
Coding
Verilog Shift Register with Test Bench
module shifter (result, value_in, direction, type, length); output [7:0] result; input [7:0] value_in; input direction;…
Verilog
Verilog Awareness
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which i…
Verilog
Verilog Awareness
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between bl…
Jitter
Clock Jitter
Clock jitter is the deviation from the ideal timing of clock transition events. Because such deviation can be detriment…
Verilog
Verilog Blocking Vs Non Blocking, Myths and Facts
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little…
Synthesis
Clock tree synthesis
Basics of Clock Tree Synthesis: The main idea is to balance the skew between endpoints. They are built with the followi…
Guidelines
Design Guidelines and Criteria for Digital Electronics
..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amoun…
State Machines
"Safe" and "Unsafe" state machines
"Safe" State Machines: If the number of states (N) is a power of 2 and you use a binary or gray-code encoding…
Metastability
Metastability
Metastability in electronic circuits Metastability is a phenomenon that occurs in digital circuits when an input signal…
Interview Questions
Synthesizable Verilog from behavioral constructs - 5
Delay statements, e.g. @(posedge clock), require careful attention if there are several in a row. If there are only del…
Interview Questions
Synthesizable Verilog from behavioral constructs - 4
When implementing Verilog tasks in modules, the best approach is to group tasks that have the same output signals into …
Interview Questions
synthesizable Verilog from behavioral constructs - 3
To modify a behavioural Verilog fork and join statement to make it synthesizable. Behavioural: command1; fork //…
Interview Questions
synthesizable Verilog from behavioral constructs - 2
Modifying a behavioural Verilog while statement to make it synthesizable. Behavioural: command1; while (x != 0) …