Interview Questions
Interview Question - Low power
You are on a team that is exploring power reduction techniques for a new design. The details of the design and implemen…
DataFlow
Dataflow Diagrams
Dataflow diagrams are data-dependency graphs where the computation is divided into clock cycles. Purpose: Provide a dis…
Models
Algorithms and High level models
For designs with significant control flow, algorithms can be described in software languages, flowcharts, abstract stat…
Interview Questions
Interview question - Fabrication, Hypothesis, Power, Process
While you are eating lunch at your regular table in the company cafeteria, a vice president sits down and starts to tal…
Interview Questions
Interview question - Clock and Voltage
Increasing clock speed without increasing power... The following are given: You need to increase the clock speed of a…
Interview Questions
Interview question - Power & Area
One day you are strolling the hallways in search of inspiration, when you bump into a person from the marketing departm…
Interview Questions
Interview question
If you were to compare a typical digital circuit from 5 years ago with a typical digital circuit today, would you find …
Interview Questions
Basic Timing - Interview question
Assume that the timing diagram shows the limits of the allowed times (either minimum or maximum). For each of the terms…
Interview Questions
Interview Questions
If you have to write your own code (i.e. you do not have a library of memory components or a special component generati…
VHDL
Comparison of VHDL to Other Hardware Description Languages
VHDL Disadvantages VHDL is verbose, complicated and confusing Many different ways of saying the same thing Constructs t…
Power
Power Analysis and Power-Aware Design - Part 1
Importance of Power and Energy: Laptops, PDA, cell-phones, etc —obvious! For microprocessors in personal computers, eve…
Learning
Delay Modelling and Coding Guidelines
In digital logic design, there are different types of delay modeling. Some of the commonly used delay modeling techniqu…
Wishes
New Year's Wishes
May you get a clean bill of health from your dentist, your cardiologist, your gastro-enterologist, your urologist, your…
Editorial
Future Trends!!
How long do you think DVDs have around? 20 years? 10 years? Actually, they have only been around for about seven years,…
GLS
Gate Level Simulation, Part - II
Gate level simulation is used in the late design phase to increase the level of confidence about a design implementat…
Verilog
Verilog rules that can save your breath !
This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rul…
Embedded
Embedded System Design: A Unified Hardware/Software Introduction
Some web resources, references, labs, and slides. http://esd.cs.ucr.edu/
Synthesis
Synthesis
Logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (…
Verilog Tutorial
Comprehensive Verilog Tutorials - Introduction
The history of the Verilog HDL goes back to the 1980s, when Gateway Design Automation developed Verilog-XL logic simula…
Verilog Tutorial
Comprehensive Verilog Tutorials - Welcome
This is an Introductory & Comprehensive Verilog Course, which covers.. Modeling Designs for Digital Simulation. Mod…
Sponsors
Sponsors
Be a sponsor & Support this Blog Some of our Proud Sponsors: VLSIChipDesign Checkout how much a Text-Link is worth …
Updates
Invitation to be a contributor on this blog!
We are happy to invite you as a contributor to this blog in digital electronics. Of course, you can choose to be anonym…
Updates
Added Features!
After much awaited delay due to developments on the blogger in beta, i m happy to announce that i have successfully con…
GLS
Gate level simulation - Introduction
Gate level simulation (GLS) is a technique for verifying the functionality and timing of a digital circuit after it has…
Low Power
RTL considerations and Functional verification of low power designs
This article is about RTL in a Multi-Voltage environment and it's implication on verification. In the earlier …
Low Power
Todays Low Power Techniques
Lets take a look at the various low power techniques in use today. I would classify them into 2 categories Structu…
Low Power
Design Elements of Low Power Design
Special cells are required for implementing a Multi-Voltage design. Level Shifter Isolation Cell Enable Level Shifter…
Low Power
Infrastructure Needs for Multi-Voltage Designs
Before we start looking at implementing a Multi-Voltage design there are certain questions that need to be answered to …
Low Power
Multi Voltage magic
In the last few weeks i have been quite busy with a lot of research on low power design. There are so many tutorial…
Low Power
Vt Cells and Spacing Requirements
Multi-Vt placement/spacing concerns I was just thinking about most common concerns faced today in addressing leakage p…
Simulation
Event simulation versus cycle simulation
By popular demand: Event simulation allows the design to contain simple timing information - the delay needed for a sig…
Updates
Updates
Last 2 weeks has witnessed a sudden surge in visitors and so i decided to continue my experiments for some more time wi…
Info
NOTICE
I have found that this Blog has not attracted enough enthusiasts as expected. So due to lack of participation i m force…
Interview Questions
basic arithmetic
What are the representations for, zero in 2's compliment the most positive integer that can be represented using…
Interview Questions
Testing
You get the final chip back from the FAB. Now you do the smoke test(power up). Hopefully assuming that things are well …
Interview Questions
Significance of contamination delay in sequential circuit timing
Q: What is the significance of contamination delay in sequential circuit timing? Fact: 70-80% of designers who deal …
Interview Questions
FSM based Interview Question
Calculate the size of the ROM if the sequential element is 'n' bits wide. What is the number o…
Multi Clock
Approaches that can ease multi-clock designs
Problem 1: Metastability Solution: Use appropriate synchronizers. (please read my earlier articles to understand the …
Interview Questions
Key points in Logic Design Timing
In a synchronous design, all memory elements, flip-flops and latches, are synchronized be a master clock. A timing di…
Interview Questions
FSM Questions
Design an FSM that has 1 i/p and 1 o/p. The o/p becomes 1 and remains 1 when at least two 0's and two 1's have …