IEEE
IEEE ComSoc Complimentary online tutorials
Two Complimentary Online Tutorials Available Now… IEEE Communications Society is pleased to offer two free online tut…
mentor graphics
Your take on the Cadence-Mentor hostile takeover bid
---------- Forwarded message ---------- From: < jcooley@zeroskew.com > Date: Wed, Jun 18, 2008 at 6:02 PM Subjec…
ECO
Tool to help automate ECO creation
[Via John's Semi-Blog ] Without too much fanfare, Cadence has introduced a tool to help automate ECO creation: Cade…
Homemade VoIP Network Over Wi-Fi Routers
A blogger on The Tech Report details his research and testing of wireless voice communication options for remote mount…
Swallow this! - Infineon in takeover rumor by Samsung or Intel
[ EETimes ] has an article on rumors that Samsung and possibly Intel might be interested in taking over Infineon. If y…
Conferences
Wiretap -- The Troublemaker's Panel (DVcon)
[Via deepchip] This year's Troublemaker's Panel discussed Mike Santarini, VC's, DataQuest, Nvidea, real est…
VLIW
Tilera Releases 64-Way Chip Dev Tools
Tilera has released a Linux-based development kit for their 64-core system on a chip. The Tile64 is based on a proprie…
News
Template related issues
All issues have been fixed. Recommended Browser's: Firefox 2 or higher IE 7 or higher The Team, The Digital Electro…
Processors
Intel's 6-core Dunnington CPU coming this year, Nehalem gets official
Quad-core shmod-core Intel, we need 6 cores or more to keep our uh, web browsers snappy. While you're at it, how ab…
WiFi
Intel touts long-distance WiFi for rural areas
While some companies are busy exploring other options for bringing wireless connectivity to rural areas, Intel's ap…
Interview Questions
Top 50 Interview Questions on CPU Architecture
What is the difference between a microprocessor and a microcontroller? What are the different components of a CPU, and …
WiMAX
Tata rolls out "world's largest" commercial WiMAX network in India
It seems as if Tata Communications is out to one-up BSNL -- or at least claim its share of the limelight, anyway. More …
News
3G iPhone rumored to be Infineon-powered, hitting "mid-year"
Hold the presses: Apple may be releasing a new iPhone this year... with 3G! Crazy, we know. The latest iteration of thi…
Technology
Intel's 6-core Xeon and Nehalem CPU info leaked
Intel's had its new processor plans slipped out to the public thanks to Sun, according to DailyTech. Details on th…
FMEA
FMEA - Failure Mode and Effects Analysis - Part 1
Failure Mode and Effects Analysis (FMEA) : A procedure for analysis of potential failure modes within a system for the …
Breakthrough
Low Voltage Is Key To Energy-Efficient Chip - Part II
I have managed to gather a real doc on the recently announced low voltage chip... These are some of the important detai…
TI
Mobile TV heats up with Broadcom's 65-nm SOC
The official news is out! Broadcom has just announced a monolithic digital CMOS mobile TV receiver/demodulator, that re…
TI
TI reveals details of 45-nm process
Rumors had been rampant for the past 3 months or so that TI had stopped development on the 45 nm node and moved on to 4…
Breakthrough
Low Voltage Is Key To Energy-Efficient Chip
News in from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designe…
DAC 2008
The Digital Electronics Blog at Design Automation Conference (DAC)
The Design Automation Conference (DAC) website has listed this Blog in the Industry Blogs Section on the home page. Th…
Good Technology Business Blogs
Sramana Mitra 's Take on Technology Business Blogs... TechCrunch : TechCrunch reports on new technology companies …
Seminars
The Future of High Performance Memory!
Rambus India Design Seminars The Future of High Performance Memory Designs 21 February 2008 | The Leela Palac…
DesignCon 2008
DesignCon 2008
Your Design Connection Awaits! DesignCon attracts engineering professionals from various levels and disciplines and r…
TAU 2008
TAU 2008
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop) w…
DAC 2008
ACM/EDAC/IEEE Design Automation Conference 2008
The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for …
OVM Available Now!!
The OVM is now available for download from the new OVM website . The OVM is based on the IEEE 1800 SystemVerilog stand…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 7
Hints Avoid more package references than needed Keep all objects and subprograms in the nearest possible scope Keep loc…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 6
To Avoid common Warnings Store each VHDL unit into a separate file except package header and body Signal assignments fo…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 5
Critical Policies to Keep note! Balance clock to delta accuracy Pull-ups and pull-downs have to be modeled on chip leve…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 4
To Avoid common Errors A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 3
Portability Language for modeling should be VHDL-87 VHDL-93 keywords should not be used Verilog keywords should not be…
IFIP/IEEE VLSI-SoC 2008 International Conference, 16th International Conference on Very Large Scale Integration
IFIP/IEEE VLSI-SoC 2008 International Conference 16th International Conference on Very Large Scale Integration Oct…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 2
When Compiling (VHDL): A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 1
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It…
Case analysis
What is case analysis?
Case analysis lets you perform timing analysis using logic constants or logic transitions on ports or pins to limit the…
Timing
Register re-timing
Register retiming is a sequential optimization technique that moves registers through the combinational logic gates of …
Soft Macro
Soft Macro Vs Hard Macro?
Last updated: 26th August 2023 Total Views: 22378 In this blog post, we will compare and contrast two types of macros …
Delays
Delays in ASIC/VLSI design
Source Delay/Latency, Network Delay/Latency, Insertion Delay, Transition Delay/Slew, Path Delay, Net delay, Wire delay,…
Interview Questions
Latch based Interview Question
Latch-based designs are sometimes used for high-speed digital circuits. One possible configuration places combinational…
Interview Questions
NVIDIA Interview Question
Two stages are added to the pipeline discussed in the earlier post to form the circuit shown below. 1. …
Interview Questions
NVIDIA Interview Question
Your task is to develop a method to reduce the power consumption of the 2-stage image processing pipeline shown below (…