Markets
Why the layoffs if we're still profitable?
This is the most common question being asked among engineers and rather should be asking if you are not. EDN Executive …
Opinions
Semiconductor Job Outlook
With big players joining the fray in job cuts, the semiconductor job outlook looks atrociously grim. The recent figures…
free
Wikipedia: The Missing Manual
Wikipedia: The Missing Manual is a popular how-to book on Wikipedia that has all the information you need to get start…
free
The Seven Habits of Highly Effective People
You can Download a free copy of "The Seven Habits of Highly Effective People" audio book by going to audible.…
VLSI Society of India
Upcoming Events: Automated Design of Digital Microfluidic Lab-on-Chip
An event of VLSI Society of India ! Seminar on: Automated Design of Digital Microfluidic Lab-on-Chip (Connecting Bioch…
free
Free E-Book Download - Only RSS Subscribers!
Subscribe to our RSS Feed to download your copy of the E-Book. E-Book: The Digital Signal Processing Handbook. Read fu…
Lifetime Achievements
What will be your engineering legacy?
It is no easy task to record the achievements of individual engineers nowadays. But looking at the past achievements an…
Top 10
The Top 10 power management 'How To' design articles of 2008
EETimes has published an article on the Top 10 Power Management articles of 2008. {Follow Here}
Satisfaction
Salary and Job Satisfaction
I picked up this survey from the web and thought should share. What do you think? [Article Here]
Contact
Advertise with us!
Many companies are catching on to the fact that bloggers can provide an effective way to create buzz (viral marketing) …
Top 10
Top Ten Chip Companies 2008
Based on Revenue numbers from iSuppli in $Bn. 1. Intel - 34 2. Samsung - 18 3. TI - 12 4. Toshiba - 11 5. ST - 10.7 6. …
Semicoductor
How to run a semiconductor company?
Anybody in this industry would agree that there are 3 things that are critical for its success. 1. Quick adaptation of …
Top 10
Top 10 Ways to Save Money in a Recession
Times are tough, money's tight, and nobody should be spending more than they need. If you think you've exhauste…
VITAL
VITAL and its Origins!
Verilog started out as a proprietary simulator in 1984 and enjoyed considerable success due to its C like syntax. In 19…
Comments
Post a link in your comments!
I am sure you have been reading this blog and did you decide to comment? In writing your comment, you may find a need t…
Memory Faults
Memories - Memory Faults - Part 4
As memories grow larger, with more memory cells packed into an ever-shrinking die area, the cost to manufacture a die r…
Memory Patterns
Memories - Test Patterns & Algorithms - Part 3
In this section some classical, or legacy, memory test algorithms will be examined. Memory test algorithms fall into tw…
Topics
Launch - I have something to explain (updated)
Hello Readers: Today we are happy to announce the launch of our new open invitation based column called "I have so…
Memory Types
Memories - Memory Types - Part 2
Semiconductor memories are characterized according to the following properties: Serial or random access, Volatile or no…
Memories
Memories - Introduction - Part 1
Memories are pervasive in digital computing. Consider, the personal computer which has a main memory, video memory, tra…
Top 10
TOP 10 IC DESIGN LINKS OF 2008
[Via ednmag] Fister, others out at Cadence Will new ideas dim the future of FPGAs? Structured ASICs and microcontroller…
Google Group
Got a question? Ask in the Forums
Blogger's blogging platform is great but is not powerful enough to support discussions of any kind. We had evaluate…
Updates
Blog Updates, Top 10 Features additions!
Hello Reader, In this New year we are happy to announce a significantly redesigned blog which gives more flexibility an…
Testing
The Economics of Test, Part - IV
Detecting a defective unit is often only part of the job. Another important aspect of test economics that must be consi…
Testing
The Economics of Test, Part - III
However, if devices are tested, feature sizes can be reduced and more die will fit on each wafer. Even after the die ar…
I have something to explain
The Economics of Test, Part - II
The table depicted shows test cost broken down into four categories some of which are one-time, non recurring costs whe…
I have something to explain
The Economics of Test, Part - I
What are the factors that influence the cost of test? Quality and test costs are related, but they are not inverse of o…
TCL for EDA
TCL for EDA - A repository Free TCL/TK tools, scripts for EDA...
http://www.tclforeda.org/ The TCL for EDA project is an open-source repository of TCL/TK tools, applications, scripts a…
Transport Delay
Transport delay / Inertial Delay / Delta Delay
In Verilog and VHDL, there are three types of delays that are commonly used in digital logic simulation: delta delay,…
Cycle Simulation
Cycle based simulation
New design starts continue to grow in gate count, and the amount of CPU time required to simulate these designs tends t…
Event Driven Simulation
Event driven simulation/simulator
A latch or flip-flop does not always respond to activity on its inputs. If an enable or clock is inactive, changes at t…
Linting
Linting tools
Some of the tools used for design verification of ICs have their roots in software testing. Tools for software testing …
White box testing
White box testing or Black box testing
When performing verification, the target device can be viewed as a white box or a black box. During whitebox testing, d…
Netlist
Formal Verification or EquivalenceChecking
Design verification, must show that the design, expressed at the RTL or structural level, implements the operations des…
Interview Questions
Avago Technologies (former HP group) Interview Questions
How do you minimize clock skew/ balance clock tree? Given 11 minterms and asked to derive the logic function. Given C…
Interview Questions
Hynix Semiconductor Interview Questions
How do you optimize power at various stages in the physical design flow? Power optimization is an important aspect of p…
Interview Questions
Hughes Networks Interview Questions
What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations? Explai…
Qualcomm
Qualcomm Interview Questions
RTL Design In work Design Verification In work Physical Design In building the timing constraints, do you need to const…
Interview Questions
Texas Instruments (TI) Interview Questions
How are timing constraints developed? Explain timing closure flow/methodology/issues/fixes. Explain SDF (Standard Del…
Interview Questions
ST Microelectronics - Interview Questions
What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)? What was the a…