SDRAM Memory Systems: Architecture Overview and Design Verification
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is …
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is …
Android is an open source platform built by Google that includes an operating system, middleware, and applications for …
Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide th…
Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart…
Most failures are not single-point; generally a single event does not entirely account for the failure. Often multiple …
This book is intended for those who work in or provide components for industries that use digital signal processing (DS…
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the …
Many embedded system-on-a-chip (SoC) designs make use of multiple processors, but do so in an application-specific or &…
Hardware design data and design flows present unique requirements that are not met by software configuration management…
According to Mitch Weaver, corporate vice president for front-end verification at Cadence, the e verification language…
Broadcom recently announced a single-chip HSUPA baseband processor that integrates key 3G mobile technologies and will…
How many times in the course of a project have you heard of the term Formal Verification? This relatively short on arti…
In this article Richard Goering talks about a software bug in Toyota Prius 2005 and after 5 years even after a through…
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cann…
Featured Tutorial: Step-By-Step Guide to Advanced Verification Tutorial!, DVcon Exhibits and Product Demos.., DVCon Pap…
This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing…
Mode details about Free Simulators are here -> https://blog.digitalelectronics.co.in/2023/03/free-hdl-simulators.ht…
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are…
This matrix illustrates (SupportNet access needed) the version compatibility between Questa SV/AFV and different versio…
DVClub is a very interesting organization. With chapters in Austin, Bangalore, Boston, Dallas, Research Triangle Park,…
Case Study:SystemVerilog VMM vs. BSV for an Ethernet MAC test bench. High-level verification languages and environment…
Today, cars can have as many as 70 electronic control units, or ECUs, based on microcontrollers (sometimes generically …
It is not completely correct to say that we have to avoid latches in our designs. In one of our recent projects we went…
By now you would have digested enough info about iPad from all the overflowing blogs and sites that are covering Apple…
A CPU has a memory unit with 32-bit instructions and a register file with 32 registers. The instruction set consists of…
Draw the circuit diagram for barrel-shifter that can shift 3 bits in either direction. The shifter should take 3 bits a…
In this article we will see how to create a simple Tcl script that tests for certain values on a signal and then adds b…
Over the last decade functional verification of ASIC systems has witnessed a paradigm shift in verification methodologi…
An effective verification plan encompasses a detailed description of the complete hierachical verification methodology …
Researchers from Helsinki University of Technology (Finland), University of New South Wales (Australia), and University…
For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent p…
The semiconductor industry in general demands two special skills in every engineer. One of these skills is more trivial…
VLSID 2010, Asia’s premier technical conference on VLSI design, EDA and embedded systems will be held at NIMHANS Conven…
For the most part the primary reaction is to defend yourself with a cause or justification or to just outrightly acknow…
Fedora Electronic Lab (FEL) comes to fix one big problem in the opensource community. The problem is : there is no on…
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Although all flash memories use the same basic storage cell, there are a number of ways in which the cells can be inter…
Flash memory is a type of electronic memory increasingly used in a wide range of communications, consumer, computer and…
We are excited to see that the BrainGate Neural Interface System is moving to phase-II clinical testing . BrainGate is…
Hot papers from this year's VLSI Technology Symposium include three nonvolatile memory advancements: Toshiba' …
With developed markets saturated and shifting mostly high-end handsets, and mid tier phone providers continuing to stru…
Intel has been rather successful at carving out a larger percentage of the netbook market with their low power Atom pro…
Engineers at Nokia have hatched a plan to for a system that'll charge phones using nothing more than ambient electr…
In 1965, Gordon Moore sat down to pen his article for a Electronics Magazine and this is when he saw some fundamental d…
The author ( Mark Smotherman, Associate Professor, School of Computing, Clemson University ) makes an effort to list th…
A Video Lecture from UC Berkeley on Analog-Digital Interfaces! Analysis and Design of VLSI Analog-Digital Interface Int…
In this SpyGlass(R) webinar, Atrenta experts will take you through the highlights of the new release and cover the foll…
Virtual Component Exchange (VCX) is a web-based, regulated trading exchange for semiconductor virtual components or int…