TechOnline
Reduce Power, Area and Routing Congestion
This paper , using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by …
White Papers
How System-Level Trade-Offs Drive Data Converter Decisions
For both analog-to"digital converters (ADC) and digital-to"analog converters (DAC), system-level specificatio…
TechOnline
Improve Product Quality and Reliability with In-System Diagnostics
Product quality and reliability are first-order design requirements for any product development. This document describ…
TechOnline
How to Create a Touchless Slider for Human Interface Applications
Imagine being able to control electronics products at home and in the office, not with a direct touch but with the swee…
TechOnline
LTE-Advanced Technology Introduction
Since the year 2010 commercialization of the LTE technology is taking place. At the same time further enhancements of t…
White Papers
Show Me the Next-Generation HDMI
The first part of this white paper explores the basic concepts behind HDMI, the markets it serves and its leadership ro…
White Papers
A Lifecycle Approach to Quality Management
Success in ever more competitive worldwide marketplaces demands continually smarter products and systems, which in turn…
TechOnline
Designing Low Power, Multi-Primary Technology for Mobile Phone Displays
Displays have always been a major power consumer in mobile devices. In the past, one easy way to keep power demands in …
TechOnline
Major Benefits of IEEE-1149.7(Compact JTAG)
This paper provides a summary of the features and benefits from the new IEEE-1149.7 specification commonly referred to…
TechOnline
Checklist for Success with Multicore
The benefits of multicore are numerous, but to realize them you must avoid the common pitfalls by planning carefully an…
White Papers
Fast, Easy, and Flexible Power for System Designers
Systems designers are having a difficult time developing power subsystems that supply all of their system's power n…
White Papers
Improve Project Success with Better Information
Are we on target? Are we within budget? Are my projects contributing effectively to my operational objectives? How well…
TechOnline
Challenges for the 28nm half node: Is the optical shrink dead?
A half-node process has been routinely used to deliver incremental improvements in process control and hardware availab…
TechOnline
Debug and Validation of High Performance Mixed Signal Designs
Modern embedded and computing systems have become progressively more powerful by incorporating high-speed buses, indust…
TechOnline
Patents database: An easy and cost effective way to perform reverse engineering for chip designers
Reverse engineering is a very common practice in semiconductor business. Companies will barely admit doing it but every…
RoHS
Best Practices for Reducing Risk through Environmental Compliance Data Collection
Complying with the variety of environmental regulations has become a challenging task for electronics OEMs (Original Eq…
TechOnline
Application Specific IP
One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP's quality. A comm…
Verification
Boosting RTL Verification with High-Level Synthesis
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creati…
TechOnline
SDRAM Memory Systems: Architecture Overview and Design Verification
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is …
TechOnline
Getting Started with Android Development for Embedded Systems
Android is an open source platform built by Google that includes an operating system, middleware, and applications for …
White Papers
Phase-locked loops (PLLs) Demystified
Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide th…
Verification
Diagnosing clock domain crossing errors in FPGAs
Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart…
TechOnline
Fantastic failures
Most failures are not single-point; generally a single event does not entirely account for the failure. Often multiple …
papers
Digital Signal Processing: A Practical Guide
This book is intended for those who work in or provide components for industries that use digital signal processing (DS…
Verification
The Art of Debugging: Make it Fail
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the …
TechOnline
Single Chip Coherent Multiprocessing
Many embedded system-on-a-chip (SoC) designs make use of multiple processors, but do so in an application-specific or &…
TechOnline
Data Management for Hardware Design Teams
Hardware design data and design flows present unique requirements that are not met by software configuration management…
Verification
e Verification language is alive and well
According to Mitch Weaver, corporate vice president for front-end verification at Cadence, the e verification language…
Smart Phones
Broadcom's smartphone on a chip
Broadcom recently announced a single-chip HSUPA baseband processor that integrates key 3G mobile technologies and will…
Theorem proving
Formal Verification: Theorem proving
How many times in the course of a project have you heard of the term Formal Verification? This relatively short on arti…
Verification
Toyota Prius 2005: An Early Warning About Verification
In this article Richard Goering talks about a software bug in Toyota Prius 2005 and after 5 years even after a through…
Verification
Motivation: What else can we talk about verification?
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cann…
Verification
Verification Sessions at DVcon 2010
Featured Tutorial: Step-By-Step Guide to Advanced Verification Tutorial!, DVcon Exhibits and Product Demos.., DVCon Pap…
Verification
Clock-Domain Crossing Verification Module
This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing…
Modelsim
ModelSim PE Student Edition - Free HDL Simulation
Mode details about Free Simulators are here -> https://blog.digitalelectronics.co.in/2023/03/free-hdl-simulators.ht…
Verification
Questa SV/AFV: Verification Methodology Kits
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are…
SupportNet
Questa Compatibility Matrix: Versions of Questa SV/AFV that work with different versions of other Mentor and open-source verification products
This matrix illustrates (SupportNet access needed) the version compatibility between Questa SV/AFV and different versio…
DVclub
Design Verification Club (DVclub)
DVClub is a very interesting organization. With chapters in Austin, Bangalore, Boston, Dallas, Research Triangle Park,…
Sponsored
Delivering synthesizable verification IP for testbences
Case Study:SystemVerilog VMM vs. BSV for an Ethernet MAC test bench. High-level verification languages and environment…
Toyota
Toyota's woes: More technology, more complexity
Today, cars can have as many as 70 electronic control units, or ECUs, based on microcontrollers (sometimes generically …
Latch
Are latches really bad for a design?
It is not completely correct to say that we have to avoid latches in our designs. In one of our recent projects we went…
PA semi
iPad and the A4 chip
By now you would have digested enough info about iPad from all the overflowing blogs and sites that are covering Apple…
Interview Questions
Interview Question on CPU design
A CPU has a memory unit with 32-bit instructions and a register file with 32 registers. The instruction set consists of…
Interview Questions
Interview Question
Draw the circuit diagram for barrel-shifter that can shift 3 bits in either direction. The shifter should take 3 bits a…
Tips and Tricks
Modelsim Tips & Tricks
In this article we will see how to create a simple Tcl script that tests for certain values on a signal and then adds b…
VIP
The world of HVLs and VIPs
Over the last decade functional verification of ASIC systems has witnessed a paradigm shift in verification methodologi…
Verification Plan
Verification Plan
An effective verification plan encompasses a detailed description of the complete hierachical verification methodology …
Size. Transistor Size
Single-atom transistor discovered
Researchers from Helsinki University of Technology (Finland), University of New South Wales (Australia), and University…
Verification
Dealing with clock jitter in DDR2/DDR3 based designs
For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent p…