Motivational Speaker - John Foley ( Former Blue Angel)
Our company today hosted a renowned motivational speaker Mr. John Foley of Blue Angels fame. The title of the talk be…
Our company today hosted a renowned motivational speaker Mr. John Foley of Blue Angels fame. The title of the talk be…
Infineon Technologies India Pvt Ltd has some openings for full time and contract positions. If you are interested in ap…
ip.access, the leading developer of femtocell and picocell solutions, and AlertMe.com, the pioneer in home energy mana…
The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL…
This new model available in black or white from June 24 has an unchanged pricing at $199 for the 16GB model and $299 fo…
The conference schedule and the registration links can be found here . With a program that is focused on helping you de…
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…
The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to …
Clock skew variation estimation is an important topic in the design and analysis of high-performance digital circuits. …
How can you quantify the impact of dummy fill on post-layout timing? Dummy fill can be inserted into a layout using SO…
Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever…
Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, ma…
How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final d…
How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?
Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage ac…
Constructing a zero-skew clock tree can be formulated as constructing a path-length balanced tree (assuming path delay …
Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a stat…
Modern clock networks include several drivers in which delays are affected by the timing of their input signal transiti…
Re-timing reduces longest combinational logic paths by relocating some of the flip-flops, both logically and physically…
This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. Thi…
This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further…
Process variation extraction needs to be design specific, and based on random field simulation, as mechanical engineeri…
Anuj, who's worked on video chips for nearly 20 years, is a great role model for all practicing engineers. He'…
Updated 28 Aug 2023: I have listed below a set of common interview questions asked mainly in interviews related to phys…
Here are five of the most insulting leadership practices , the ones that virtually guarantee a business will end up wi…
Q1: How would you speed up an ASIC design project by parallel computing? Which design stages can be distributed for pa…
Physicists at McGill University in the US now have a system where they can measure the energy involved in adding elect…
Each fall, the UW College of Engineering partners with the UW Alumni Association to present a series of free lectures …
With so much useful advise and talented career experts out there with often differing opinions, you will most likely en…
Consumer electronics remains one of the fastest growing business markets in today's world and provides many opportu…
Researchers at Duke University recently used DNA to craft tiny chips used in computers and electronic circuits . By mi…
Vancouver, WA -- Wilder Technologies has released a new family of test adaptor products for the test & measurement …
Cambridge Wireless has announced the second meeting of the popular semiconductor Special Interest Group meeting taking …
Libelium, a technology leader in distributed wireless networks, announced a new Bluetooth module for its Waspmote wirel…
VLSI Solution has announced VSIDE - the Integrated Development Environment for VSDSP Processor Family. VSIDE is an inte…
1. **For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the p…