Interview Question on Power Analysis

Interview Question on Power Analysis

Your task is to do power analysis for a circuit that sends out a one-clock-cycle pulse on the done signal once every 16…

Cyclic Redundancy Checking (CRC) - Part 2

Cyclic Redundancy Checking (CRC) - Part 2

Modulo two arithmetic is simple single-bit binary arithmetic with all carries or borrows ignored. Each digit is conside…

Cyclic Redundancy Checking (CRC) - Part 1

Cyclic Redundancy Checking (CRC) - Part 1

Error detection is an important part of communication systems when there is a chance of data getting corrupted. Whether…

Stoke Technical Seminar Series - Wireless

Stoke Technical Seminar Series - Wireless

If you live in Bangalore, India this might be of interest to you. Stoke Technical Seminar Series focus on 3G Mobile D…

10 Reasons to Customize a Processor Core

10 Reasons to Customize a Processor Core

There are plenty of really good, proven processor cores on the market today. But if you have more than simple control t…

Broadcom buys femtocell chip maker

Broadcom buys femtocell chip maker

Femtocells are small, low power cellular base stations that extend coverage indoors where signals are weak. Broadcom Co…

Five good, five bad signs for IC market

Five good, five bad signs for IC market

We are in the fourth quarter and the outlook is cloudy for the rest of 2010 and heading into 2011. Here are some good …

GlobalFoundries tech park in trouble?

GlobalFoundries tech park in trouble?

A New York state agency plans to take over a technology park that houses the new 300-mm fab owned by U.S. silicon foun…

Is Intel prepping up for 450mm wafer sizes?

Is Intel prepping up for 450mm wafer sizes?

Is Intel preparing to push the issue with regard to its desire to move to 450-mm wafer sizes? One analyst thinks so . W…

Intel buys Infineon wireless

Intel buys Infineon wireless

As per the management email sent to Infineon employees this morning, Infineon and Intel have signed the contracts relat…

High-Level Synthesis Blue Book

High-Level Synthesis Blue Book

The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL…

High-def iPhone 4

This new model available in black or white from June 24 has an unchanged pricing at $199 for the 16GB model and $299 fo…

SNUG India 2010 Registrations Open

SNUG India 2010 Registrations Open

The conference schedule and the registration links can be found here . With a program that is focused on helping you de…

Clock network design

Clock network design

In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…

IR drop driven placement

IR drop driven placement

The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to …

Clock skew variation estimation

Clock skew variation estimation

Clock skew variation estimation is an important topic in the design and analysis of high-performance digital circuits. …

Impact of dummy fill on timing

Impact of dummy fill on timing

How can you quantify the impact of dummy fill on post-layout timing?  Dummy fill can be inserted into a layout using SO…

Investigation on timing analysis inaccuracies

Investigation on timing analysis inaccuracies

Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, ma…

Distributions in statistical timing

Distributions in statistical timing

How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final d…

Dynamic power supply

Dynamic power supply

Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage ac…

Clock tree theory

Clock tree theory

Constructing a zero-skew clock tree can be formulated as constructing a path-length balanced tree (assuming path delay …

Statistical clock tree design

Statistical clock tree design

Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a stat…

Clock driver input alignment

Clock driver input alignment

Modern clock networks include several drivers in which delays are affected by the timing of their input signal transiti…

Transistor level technology remapping

Transistor level technology remapping

This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. Thi…

Transistor sizing / multi-Vt design

Transistor sizing / multi-Vt design

This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further…

Process variation extraction

Process variation extraction

Process variation extraction needs to be design specific, and based on random field simulation, as mechanical engineeri…

Backend physical design Interview Questions

Backend physical design Interview Questions

Updated 28 Aug 2023: I have listed below a set of common interview questions asked mainly in interviews related to phys…

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