A flip-flop is Edge sensitive: Output only changes on rising (or falling) edge of clock.
A latch is Level sensitive: Output changes whenever clock/Enable is high (or low)
A common implementation of a flip-flop is a pair of latches (Master/Slave flop).
Latches are sometimes called “transparent latches”, because they are transparent (input directly connected to output) when the clock is high.
The clock to a latch is primarily called the “enable”.
For more information have a look at the picture below.
- Use flops, not latches
- Latch-based designs are susceptible to timing problems
- The transparent phase of a latch can let a signal “leak” through a latch — causing the signal to affect the output one clock cycle too early
- It’s possible for a latch-based circuit to simulate correctly, but not work in real hardware, because the timing delays on the real hardware don’t match those predicted in synthesis
- Limit yourself to D-type flip-flops
- Some FPGA and ASIC cell libraries include only D-type flip flops. Others, such as Altera’s APEX FPGAs, can be configured as D, T, JK, or SR flip-flops.
- For every signal in your design, know whether it should be a flip-flop or combinational. Examine the log file e.g. dc shell.log to see if the flip-flops in your circuit match your expectations, and to check that you don’t have any latches in your design.
- Do not assign a signal to itself (e.g. a <= a; is bad). If the signal is a flop, use an enable to cause the signal to hold its value. If the signal is combinational, then assigning a signal to itself will cause combinational loops, which are very bad.
- Flops with Waits and Ifs
- Flops with Synchronous Reset
- Flops with Chip-Enable
- Flops with Chip-Enable and Mux on Input
- Flops with Chip-Enable, Mux's, and Reset