Comparison of VHDL to Other Hardware Description Languages

VHDL Disadvantages
  • VHDL is verbose, complicated and confusing
  • Many different ways of saying the same thing
  • Constructs that have similar purpose have very different syntax (case vs. select)
  • Constructs that have similar syntax have very different semantics (variables vs signals)
  • Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)
VHDL Advantages
  • VHDL supports unsynthesizable constructs that are useful in writing high-level models, testbenches and other non-hardware or non-synthesizable artifacts that we need in hardware design.
  • VHDL can be used throughout a large portion of the design process in different capacities, from specification to implementation to verification.
  • VHDL has static typechecking—many errors can be caught before synthesis and/or simulation.
  • VHDL has a rich collection of datatypes
  • VHDL is a full-featured language with a good module system (libraries and packages).
  • VHDL has a well-defined standard.
VHDL and Other Languages
  • VHDL vs Verilog
    • Verilog is a "simpler" language: smaller language, simple circuits are easier to write
    • VHDL has more features than Verilog
      • richer set of data types and strong type checking
      • VHDL offers more flexibility and expressivity for constructing large systems.
    • The VHDL Standard is more standard than the Verilog Standard
      • VHDL and Verilog have simulation-based semantics
      • Simulation vendors generally conform to VHDL standard
      • Some Verilog constructs don't simulate the same in different tools
    • VHDL is used more than Verilog in Europe and Japan
    • Verilog is used more than VHDL in North America
    • South-East Asia, India, South America - More Democratic
  • VHDL vs SystemC
    • System C looks like C —familiar syntax
    • C is often used in algorithmic descriptions of circuits, so why not try to use it for synthesizable code as well?
    • If you think VHDL is hard to synthesize, try C....
    • SystemC simulation is slower than advertised
  • VHDL vs Other Hardware Description Languages
    • Superlog: A proposed language that was based on Verilog and C. Basic core comes from Verilog. C-like extensions included to make language more expressive and powerful. Developed by the Co-Design company, but no longer under active development. Superlog has been superseded by SystemVerilog, see below.
    • SystemVerilog: A language originally proposed by Co-Design and now standardized by Accellera, an organization aimed at standardizing EDA languages. SystemVerilog is inspired by Verilog, Superlog, and System-C. SystemVerilog is a superset of Verilog aimed to support both high-level design and verification.
    • Esterelle: A language evolving from academia to commercial viability. Very clean semantics. Aimed at state machines, limited support for datapath operations.

Search capability added

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Difficulty of designing correct chips

"Everyone should get a lecture on why their first industrial design won't work in the field."

Here are few reasons getting a single system to work correctly for a few minutes in a university lab is much easier than getting thousands of systems to work correctly for months at a time in dozens of countries around the world.

1. You forgot to make your "unreachable" states transition to the initial (reset) state. Clock glitches, power surges, etc will occasionally cause your system to jump to a state that isn't defined or produce an illegal data value. When this happens, your design should reset itself, rather than crash or generatel illegal outputs.

2. You have internal registers that you can't access or test. If you can set a register you must have some way of reading the register from outside the chip.

3. Another chip controls your chip, and the other chip is buggy. All of your external control lines should be able to be disabled, so that you can isolate the source of problems.

4. Not enough decoupling capacitors on your board. The analog world is cruel and and unusual. Voltage spikes, current surges, crosstalk, etc can all corrupt the integrity of digital signals. Trying to save a few cents on decoupling capacitors can cause headaches and significant financial costs in the future.

5. You only tested your system in the lab, not in the real world. As a product, systems will need to run for months in the field, simulation and simple lab testing won't catch all of the weirdness of the real world.

6. You didn't adequately test the corner cases and boundary conditions. Every corner case is as important as the main case. Even if some weird event happens only once every six months, if you do not handle it correctly, the bug can still make your system unusable and unsellable.

Power Analysis and Power-Aware Design - Part 1

Importance of Power and Energy:
  1. Laptops, PDA, cell-phones, etc —obvious!
  2. For microprocessors in personal computers, every watt above 40W adds $1 to manufacturing cost.
  3. Approx 25% of operating expense of server farm goes to energy bills.
  4. Sandia Labs had to build a special sub-station when they took delivery of Teraflops massively parallel supercomputer (over 9000 Pentium Pros)
  5. High-speed microprocessors today can run so hot that they will damage themselves—Athlon reliability problems, Pentium 4 processor thermal throttling
  6. Future power viruses: cell phone viruses cause cell phone to run in full power mode
Most people talk about "power" reduction, but sometimes they mean "power" and sometimes "energy."
  1. Power minimization is usually about heat removal.
  2. Energy minimization is usually about battery life or energy costs.
Power Equations:
= Switching Power+Shortcircuit Power+Leakage Power
Dynamic power = Switching Power+Shortcircuit Power
Static Power = Leakage Power
  1. Dynamic Power dependent upon clock speed
  2. Switching Power useful —charges/discharges transistors
  3. Short Circuit Power not useful —both N and P transistors are on
  4. Static Power independent of clock speed
  5. Leakage Power not useful —leaks around transistor
Dynamic power is proportional to how often signals change their value (switching)
  • Roughly 20% of signals switch during a clock cycle.
  • Need to take glitches into account when calculating activity factor. Glitches increase the activity factor.
  • Equations for dynamic power contain clock speed and activity factor.
Some power reduction techniques:
  • Analog
    • Parameters to work with:
      • capacitance for example, Silicon on Insulator (SOI)
      • resistance for example, copper wires
      • voltage low-voltage circuits
    • Techniques:
      • dual-VDD Two different supply voltages: high voltage for performance-critical portions of design, low voltage for remainder of circuit. Alternatively, can vary voltage over time: high voltage when running performance-critical software and low voltage when running software that is less sensitive to performance.
      • dual-Vt Two different threshold voltages: transistors with low threshold voltage for performance-critical portions of design (can switch more quickly, but more leakage power), transistors with high threshold voltage for remainder of circuit (switches more slowly, but reduces leakage power).
      • exotic circuits Special flops, latches, and combinational circuitry that run at a high frequency while minimizing power
      • adiabatic circuits Special circuitry that consumes power on 0 - 1 transitions, but not 1 - 0 transitions. These sacrifice performance for reduced power.
      • clock trees Up to 30% of total power can be consumed in clock generation and clock tree
  • Digital
    • Parameters to work with:
      • capacitance (number of gates)
      • activity factor
      • clock frequency
    • Techniques:
      • multiple clocks Put a high speed clock in performance-critical parts of design and a low speed clock for remainder of circuit
      • clock gating Turn off clock to portions of a chip when it's not being used
      • data encoding Gray coding vs one-hot vs fully encoded vs ...
      • glitch reduction Adjust circuit delays or add redundant circuitry to reduce or eliminate glitches.
      • asynchronous circuits Get rid of clocks altogether....

AGLOCO - Own the Internet

AGLOCO: The Internet's First Economic Network, that enables you to earn while you browse.

Today’s hottest Internet businesses are all about the power of social networks. Companies like MySpace, Facebook, and YouTube have become worth billions because businesses have realized that these social networks are generating huge advertising and marketing opportunities. As these social networks grow, the economic potential for its owners – and the advertisers who target the site’s users – is remarkable.

It was from this question that AGLOCO set out to create the Internet’s first Economic Network, harnessing the power of Internet-based social networks to directly benefit the Members who help to create the community.

Becoming a member of AGLOCO is as simple as completing a brief sign-up page (name, age, location and email address.). Once you’re a Member, you will be asked to then download the Viewbar™ software.
AGLOCO makes money for its Members in many ways
  • Search: Every time you use the Viewbar™ to do an Internet search, AGLOCO earns money from the search engine providers. (For example, Google pays as much as $0.10 on average for each search that is directed to its search engine.)
  • Advertising: The Viewbar™ itself displays ads that are targeted based upon the websites you’re visiting. When you click on an ad and make a purchase, AGLOCO receives a referral fee, which we pass on to our Members. (Please note: Individual members do not receive any compensation for clicking on ads in the Viewbar™, and the Viewbar™ can detect if someone is clicking ads in a fraudulent manner.)
  • Transaction commissions: Many major retailers pay commissions when you refer customers who make a purchase. AGLOCO collects that commission and passes it on to our members. (For example, Amazon pays an 8.5% commission to most websites who refer customers, and has cut deals for even larger percentages. The bigger the AGLOCO community, the better commission we can negotiate for our Members.)
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AGLOCO Members make money in four ways.
  • Members earn a monthly share of the AGLOCO revenue based on the use of the AGLOCO Viewbar™ that month.
  • Members earn part of the company based on the use of the AGLOCO Viewbar™ that month (currently a maximum of five hours are rewarded). Click here for details.
  • Members who use our referral system to help build the AGLOCO network will earn more. (AGLOCO only has significant value as a large network and people who help build it should be rewarded. – We also feel that the early users who told friends about YouTube or MySpace or even Google probably deserved something too, but no referral system was available to record their work).
  • Members will also get a share of any commissions AGLOCO gets when a Member purchases a product or service from an AGLOCO Sponsor company.
Why should I join now?
  • First, it costs nothing to Join and takes less than one minute.
  • Second, you can help build the AGLOCO community by recruiting new Members TODAY.
  • Right now, inviting your friends to join AGLOCO is as easy and productive as it will ever be – but you need to invite your friends before someone else beats you to them.
  • Remember, the bigger the AGLOCO community, the more attractive AGLOCO is to potential business partners and advertisers.
    • Recruit your friends and family by contacting them through email. (But remember we have a strict anti-spam policy.)
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Be a part of the Internet’s first Member-Owned Economic Community.
Join AGLOCO - Own the Internet!