Acceleration And Emulation – Why HW/SW Integration Needs Both

Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play. In our earlier post we reflected on the Cadence rollout of Palladium XP, a verification computing platform that unifies acceleration capabilities from the Incisive Xtreme product line with Incisive Palladium emulation, incorporating some of the strongest capabilities from each platform.  You can read the press release here, but in his blog Richard Goering looks at the larger story behind the announcement. Why put acceleration and emulation in a single environment? What role does either play in hardware/software integration? And how do we define "acceleration" and "emulation," anyway?

Nokia N8 is official: Priced €370 ($494)

Nokia's N8 is now official would see a launch during April. With a packed design that includes a 12 megapixel camera (with Carl Zeiss optics and a Xenon flash), 3.5-inch capacitive touchscreen, HDMI output, 16GB of internal storage, a microSD expansion slot, HD video recording, access to Ovi Store apps, free Ovi Maps walk and drive navigation, and of course, the company's new Symbian3 operating system. The N8 boasts multiple, personalizable homescreens "which can be loaded with apps and widgets," native multitasking, support for multitouch gestures and integration with the Qt software development environment. It'll ship in a variety of hues, with availability pegged for "select markets" in Q3 for €370 ($494) without any subsidies involved.

Cadence Debuts Verification Computing Platform

Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/ software environment faster and produce better quality embedded systems in a shorter time.

Cadence Palladium XP supports design configurations up to 2 billion gates, delivering performance up to 4MHz and supporting up to 512 users simultaneously. The platform also provides unique system-level solutions, including low-power analysis and metric-driven verification.

"Our system-integration challenges require us to improve our tools and methodologies continuously. Cadence has kept pace with our requirements and provided us with an excellent verification computing platform," said Narendra Konda, Director of Engineering, NVIDIA. "Cadence Palladium XP helps us design, verify and integrate the hardware and software components of our advanced graphics processing unit (GPU) better than ever to stay at the top of our game."

The Palladium XP verification computing platform provides developers a high-fidelity representation of their design so they can quickly and confidently locate and fix bugs, resulting in better-quality IP, subsystems, SOCs and system. Design teams can "hot swap" simulation with acceleration and emulation in a scalable verification environment as needed, which speeds the verification process and enables early access to testing embedded software and evaluating performance implications of different IP and/or system architectures.

"With the introduction of multicore IP platforms, ARM and our customers are facing new design requirements to integrate and run complex CPU sub-systems with software," said Dr. John Goodenough, Worldwide Director of Design Technology at ARM. "Like its predecessor, the Palladium XP verification computing platform will be a valuable validation tool for these advanced designs. Our initial trials have shown that the Palladium XP runs current ARM workloads out of the box, with the additional ability to trade off domain utilization for higher performance."


The Palladium XP verification computing platform is available now worldwide. It is offered in two configurations, XL for design teams, and GXL for enterprise-class global teams.

Gawker Media received no direct revenue from iPhone 4G scoop

In response to the iPhone 4g post i ran yesterday i got quite a few comments and i want to highlight one of them specifically! One of our readers Simon Owens got a chance recently to interview Gawker's Nick Denton and found out that despite the fact that he paid $5,000 to the people who found the iPhone, Gawker Media received no direct revenue from those millions of pageviews it received from publishing the scoop.

Google Acquires iPad Chip Maker Startup Agnilux

"Google has purchased Agnilux, a secretive chip house made up of engineers who architected the heart of the iPad, then left the company. Reuters' PEHub reported the story Tuesday night. A Google spokesman also confirmed the acquisition to 'We're pleased to welcome the Agnilux team to Google, but we don't have any additional information to share right now,' a Google spokesman said Tuesday night via email."

Lost iPhone Reveals Hardware Improvements

The internet was a-buzz this weekend after Gizmodo got its hands on what seems to be a genuine prototype fourth generation (4G) iPhone. The device was "left in a bar in Redwood City" and acquired by the Gizmodo for $5,000.
Apple was able to wipe the phone remotely before anyone could test it out, but the site's editors quickly disassembled it to discover its new hardware components. Their efforts suggest that the 4G iPhone will have several long-asked-for new features like Longer battery life, many miniaturized parts for low power consumption, a better screen, a second camera presumably for video calls and a new micro SIM.

Getting hold of the device is remarkable given Apple's paranoid attitude towards secrecy. Steve Jobs has reportedly even called to ask for it back.

Achieving Fiber-Optic Speeds over Copper Lines

A 100-year-old networking trick could boost transmissions over telephone infrastructure. Alcatel-Lucent has developed a prototype technology that could dramatically increase the speed of data communications over the copper wires that make up the majority of the world's telephone infrastructure. The technology combines three existing techniques, known as bonding, vectoring, and DSL phantom mode. It can reach speeds of 300 megabits per second at a distance of 400 meters from a communications hub, and 100 megabits per second at one kilometer. Checkout this podcast to lean more!

PCI Express-based MicroTCA Design Options

PCI Express-based MicroTCA platforms are generating more and more interest. This paper describes how small and cost-effective MicroTCA platforms can be built utilizing PCI Express. Furthermore, architecture options for multiprocessor implementations are described, including both standalone systems and clusters.

Driving Flexibility into Automotive Electronics Design

With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no longer makes business sense. This white paper discusses a process to develop an exact microcontroller for a specific application by implementing it into an Altera Cyclone IV FPGA for prototyping and volume production. Verification, software development, and field testing can be done immediately after design or even in parallel.

SuperSpeed Your SoCs with USB 3.0 IP

Since the introduction of the original USB standard in 1996, the USB interface has become one of the most successful connectivity standards. In today's highly connected world, USB connections are found in the computing, consumer, mobile, industrial and automotive segments. With the trend of increasing data storage requirements driven by applications, such as high-definition video, combined with the desire to move this data quickly between host, storage, and portable devices, it was only a matter of time before there was a need to make this well-known standard even faster. This heralds the third-generation of this ubiquitous standard—the arrival of SuperSpeed USB 3.0. This white paper provides a comparison between USB 3.0 and USB 2.0, highlighting the new capabilities and advancements that have been made with this next-generation technology.

Advertisement: HP Coupons & Coupon Codes

HP Home is the official HP website for personal computers, printing and imaging, servers and storage products for consumers. is your source for up-to-date HP laptop coupons, deals, sales and promotional offers. They update their offers daily so you don't miss a single bargain. Be sure to check in early and often, HP is one of our favorite retailers, so when they have a clearance sale or a great coupon, CouponMountain immediately uploads them to their site so you don't miss a deal! 

Improving I/O Virtualization Performance with PCI Express

Virtualization technology has been used in high-end servers for quite some time. The evolution of virtualization has brought with it the desire to reduce the software (S/W) overhead portion of virtualization, particularly for I/O devices. This paper will begin with an introduction to the general concepts of virtualization and I/O virtualization. It will then discuss how I/O virtualization is addressed within the PCI Express specification and the changes required to add I/O virtualization support to an existing PCI Express interface. Additional PCI Express topics covered include: Single-Root I/O Virtualization (SR-IOV), Function Level Reset (FLR), Alternative Routing ID (ARI) and Address Translation Services (ATS).

A Cost Effective Way to Design Next Generation Communications Infrastructure Equipment

This white paper introduces a new category of programmable logic devices, the Tabula ABAX family based on Spacetime architecture, and shows how such devices are well suited for the design and solution requirements for next generation communications infrastructure equipment.

Stay in control of schedules and costs when requirements change

Organizations need to know how changing requirements in a complex system will affect development. An effective change management process can help you better identify how alterations will affect cost and schedule so you can keep them in control. Read this white paper to learn ways to keep schedules and costs in line.

At-Speed and Advanced Fault Models for Achieving High Quality Test

With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed testing is a requirement to achieve high quality test results. In addition, new advanced fault models are also available to improve defect detection and lower DPM rates. Advanced at-speed test capabilities and some new fault models are described in this paper.

SDRAM Memory Systems: Architecture Overview and Design Verification

DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is used in a wide variety of memory system designs for computers and embedded systems. This DRAM memory primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview for memory design improvement through verification.

Protect Your FPGA Against Piracy: Cost-Effective Authentication Scheme Protects IP in SRAM-Based FPGA Designs

This application note describes FPGAs (field-programmable gate arrays) and how they can hold the key functions and the intellectual property (IP) of a system. It discusses ways to protect IP against piracy. SHA-1 challenge-and-response authentication is judged as the most secure methodology. This document presents a cost-effective authentication scheme that protects IP in SRAM-based FPGA designs. The DS28E01 and DS28CN01 1-Wire devices are featured.

Restrictive Design Rules and Their Impact on 22nm Design and Physical Verification

Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, and thus impacts both performance and yield of advanced node chips. To ensure the manufacturability and performance of chips at 22nm, one approach the industry is considering is restrictive design&mash;limiting the type and placement of features used in designs. Gridding of critical layers significantly reduces the total physical design space available and makes restrictive design possible. This paper examines the basics of gridding, the requirements for restrictive gridded design, and the automated methods for accurate checking of Restrictive Design Rules (RDRs). Resolving the debug challenges associated with the implementation of checking restrictive design and grid rules is also discussed.

Useful links for Electronics Hobbyists

A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration

This article provides a comprehensive methodology that highlights the best practices for mixed-language design integration and automatically comes up with an option for designers to select the optimal method for integration.
There are broadly five ways of making mixed-language connections. Pros and cons of each of these approaches and their comparison is described in terms of the usage scenarios, performance implications of using one versus the other, delta cycle value update concerns, and more. A step-by-step guideline based on decision-making trees that designers can follow to help them decide which approach best suits their particular mixed-language integration scenario is also discussed.

10 questions to ask when choosing a virtualization solution

Many embedded system designers are considering adopting virtualization technology in their applications, and for good reason. Benefits such as hardware cost savings, isolation and footprint reduction make virtualization an attractive option. This article attempts to ease the process by posing 10 important questions that any embedded engineer or manager considering should weigh carefully.

Infineon India Walk-in Interviews (17 April 2010, Saturday)

Infineon provides semiconductor and system solutions, focusing on three central needs of our modern society: energy efficiency, communications and security. With some 25,000 employees worldwide (as of Jan, 2010), Infineon achieved 3.027 billion euros in sale in the 2009 fiscal year. Strong technology portfolio with about 22,900 patents and patent applications; more than 30 major R&D locations.

The Walk-in Interviews will be held between 10:00 AM and 4:00 PM @ Hotel Royal Orchid, Old Airport Road, Bangalore - 8. Please see attached flyer for more details!!

List of VLSI and related Conferences

The following is a list of conferences specific to the VLSI industry. It was earlier part of a widget on the sidebar but is now moved as a post that can be accessible through rss feeds!

Post a Job on The Digital Electronics Blog

Now you can post a job on this blog for as low as $15/Week or $30/Month! This blog receives approx 25,000 page views a month and there is no better and cost effective opportunity than now to reach our diverse reader base. All payments will be accepted through Paypal. Please send in your requirements with a summary of the job description (approx 3 lines) followed by a detailed description. Please don't forget to include your contact information at the bottom.

Pain Killers for the Fixed-Point Design Flow

Taking a floating-point representation of an algorithm into a fixed-point representation is an integral step on the path towards implementation. Unfortunately, it is known to be time-consuming, tedious and error prone. This paper from synopsys describes proven methodologies on how to overcome the hurdles, including many useful tips to get you to results faster.

High level analysis of false paths

Sometimes the delay through a component is dependent upon the values on signals. This is because different paths in the circuit have different delays and some input values will prevent some paths from being exercised. Here are two simple examples:
  1. In a ripple-carry adder, if a carry out of the MSB is generated from the least significant bit, then it will take longer for the output to stabilize than if no carries generated at all.
  2. In a state machine using a one-hot state encoding, false paths might exist when more than one state bit is a '1'.
Because of these effects, static timing analysis might be overly conservative and predict a delay that is greater than you will experience in practice. The most accurate delay analysis requires looking at the actual data values that will occur in practice. Conversely, a timing simulation may not demonstrate the actual slowest behaviour of your circuit: if you don't ever generate a carry from LSB to MSB, then you'll never exercise the critical path in your adder.

Words of wisdom

The analysis of critical paths and false paths assumes that all inputs change values at exactly the same time. Timing differences between inputs are modelled by the skew parameter in timing analysis.

Words of wisdom

To exercise a path, only one inputs needs to change. Stated another way, if a path cannot be exercised by toggling one input, then the path cannot be exercised by toggling more than one input.

MIPI & SoC Integration Lunch & Learn Seminar

Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is designed to provide the latest information about MIPI standards, how to design-in an optimized MIPI solution, and how to develop an effective verification strategy for MIPI System-on-Chip (SoC) integration success!
Seating is limited - Register Now

Wednesday, April 21, 2010                    This is a Free Educational Event
Cadence Design Systems                      Registration: 10:00 am - 10:30 am
2655 Seely Avenue                                Seminar: 10:30 am - 1:00 pm
Building 10 Auditorium                            Lunch Will Be Served  
San Jose, CA  95134
(off Montague Expressway near 880)
Can't Make It?
Here's an Online Solution:
Cadence provides online self-guided Hands-On trials of Verification IP and tools for you to test drive at your desk - no downloads, no installation, and no licenses to manage.

Advanced On-Chip Variation (OCV) in PrimeTime

This application note from synopsys describes the advanced on-chip variation (OCV) solution in PrimeTime, including the recommended usage flow, and also provides an example script. The information described in this document is valid for PrimeTime versions starting with B-2008.12.

Memory Management Technique Speeds Apps By 20%

A paper (PDF) to be presented later this month at the IEEE International Parallel and Distributed Processing Symposium in Atlanta describes a new approach to memory management that allows software applications to run up to 20% faster on multicore processors. Yan Solihin, associate professor of electrical and computer engineering at NCSU and co-author of the paper, says that using the technique is just a matter of linking to a library in a program that makes heavy use of memory allocation. The technique could be especially valuable for programs that are difficult to parallelize, such as word processors and Web browsers. {Via Slashdot}

Enabling Rapid, Reliable Deployment of IP into System Designs

This webcast highlights The SPIRIT Consortium's new IP-XACT 1.4 specification which expands the range of IP that can be used in an IP-XACT Design Environment and targets new applications, specifically those dealing with transactional modeling and advanced verification methodologies. IP-XACT 1.4 benefits include documentation of all aspects of IP using XML databook format, documentation of models in a quantifiable and language- independent way, and enables designers to deploy specialist knowledge in their designs.

Words of wisdom

Cycle Simulation – This technique computes the steady state response of the circuit at each clock cycle boundary, not taking into account detailed circuit timing. No concept of delta cycle.

Words of wisdom

Elaboration of Declarations - Type consistency, etc done through following the rules that govern the declaration and initialization of signals and variables.


Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions.

Splint Annotation-Assisted Lightweight Static Checking

Splint is a tool for statically checking C programs for security vulnerabilities and coding mistakes. With minimal effort, Splint can be used as a better lint. If additional effort is invested adding annotations to programs, Splint can perform stronger checking than can be done by any standard lint.

Source Navigator for Verilog

Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog files. It parses Verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minutes of compiling.

Source Navigator was developed by Cygnus Software as a commercial IDE (Integrated Development Environment) for software engineers and was later released under the GPL by Red Hat. Source Navigator supports many languages including C, C++, Tcl, Java, Fortran, and COBOL. There are so many similar products for software engineers, but almost nothing available for hardware engineers using languages such as Verilog. By adding a Verilog parser to Source Navigator hardware engineers can now enjoy the same high quality software.

Comit-TX Verilog Testbench Extractor

Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench. Comit-TX, with the extracted testbench, enables the module's replacement to be verified in a stand-alone basis in an environment identical to its final working environment, without having to simulate the entire system.

Incisive Conformal ASIC

With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It's also production-proven with more physical design closure tools, advanced synthesis tools, ASIC libraries, and IP cores than any other formal verification tool. Many EDA tool vendors rely on Conformal ASIC as an independent standard within their regression suites to verify the results that their own tools produce.

Key Features:
    * Minimizes re-spin risk by providing complete verification coverage
    * Reduces verification time significantly by verifying multi-million gate designs by orders of magnitude faster than traditional gate-level simulation
    * Independent verification technology decreases the risk of missing critical bugs
    * Faster, more accurate bug detection and correction throughout the entire design flow
    * Provides capacity to handle designs of tens of millions of gates
    * Eliminates functional clock domain crossing problems before simulation
    * Easy to learn and easy to use
    * Structural checks perform bus checks for data conflicts, set-reset exclusivity checks, and multi-port latch contention checks
    * Clock domain checks perform synchronization validation and data stability checks
    * Full cross-highlighting between debug, schematic, and RTL source code windows

System Architect for micro-architecture performance analysis and optimization during functional simulation

System Architect is comprised of a set of powerful, on-demand SystemC-compliant functions and analysis tools that enable micro-architecture performance analysis and optimization during functional simulation. The analysis provides a wide range of valuable information showing how to improve performance and power utilization. Seamlessly linked with Summit's Vista IDE , System Architect enables effective and rapid analysis of system performance and architectural tradeoffs using C and SystemC.

The System Architect API function set can be instrumented into any functional code to track tokens of data, log states and attributes. Textual reports and visualization tools allow designers to analyze actual key performance metrics, such as bus contention, memory utilization, and SW instruction distribution - all during standard functional simulation. These metrics are critical for analyzing micro-architecture bottlenecks, bandwidth limitations, and power tradeoffs.
Key Features:

   * On-demand SystemC-compliant API functions
   * Advanced textual and graphical reports
   * Analysis of data throughput and communication latencies
   * Dynamic resource utilization analysis (such as memories and FIFO's)
   * Software task distribution and processor utilization reports
   * Hardware/Software tradeoff analysis

nECO for Verdi and Debussy debug systems

nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug systems accelerate users' understanding of complex designs to improve design, verification, and debug productivity. nECO adds the ability to isolate logic that needs to be changed in a flattened schematic, make the necessary changes, and write the modified design to a new netlist file.

Functionally debug in RTL source using Identify RTL Debugger

The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than RTL simulators, and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW designs. Identify software allows designers to directly select signals and conditions in their RTL source code for debugging and the results are viewed directly in the RTL source code. The Identify tool can also save results in standard VCD format that can be used with most waveform viewers.

Key Features:
* Allows the designer to insert debug logic and view results directly in the RTL source code.
* Allows FPGA to run at normal design speed, but still allows debug access.
* Allows the designer to set triggers on signals and their values (data path), as well as trigger on RTL code branches such as CASE and IF statements.
* Allows the designer to view the captured data from the FPGA in almost any waveform display. Provides standard VCD output for results.
* Provides VHDL models for waveform data with all the type information and data included allowing the designer to view results in a waveform display complete with all the VHDL type information that they want to see.

Gatevision for Netlist debugging

GateVision  is a standalone graphical netlist analyzer that allows intuitive design navigation, schematic viewing, logic cone extraction, interactive logic cone viewing, and design documentation. GateVision's easy-to-read schematics and schematic fragments provide excellent debug support and accelerate the debug process.

Key Features:

   * On-the-fly schematic creation results in very high speed and capacity
   * Automatically extracts logic cones from user-defined reference points, and shows just the important portion of the circuit
   * Interactive logic cone navigation Allows compelling signal path tracing through the complete design hierarchy
   * Search-and-show capability allows easy location of specific objects shortens debug time
   * Design hierarchy browser provides easy navigation through the design hierarchy and gives compact hierarchy overview
   * Object cross-probing highlights selected objects in all design views (schematic, logic cone and HDL view) and shortens debug time
   * Context-sensitive menus and easy-to-use GUI
   * Verilog and EDIF netlist interface allows integration s into almost any design flow
   * Userware API allows addition of custom features

Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route

Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a two-fold speed-up in the synthesis and physical implementation flow.

To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce "physical guidance" to Synopsys' flagship place-and-route solution, IC Compiler, tightening timing and area correlation to 5% while speed IC Compiler's placement phase by 1.5 times (1.5X). A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. In addition, Design Compiler's new scalable infrastructure tuned for multicore processors yields 2X faster synthesis runtimes on four cores. These new Design Compiler 2010 productivity improvements will be highlighted today by users at the Synopsys Users Group (SNUG) meeting in San Jose, California.

"Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace," said Hitoshi Sugihara, Department Manager, DFM & Digital EDA Technology Development at Renesas Technology Corp. "With the new physical guidance extension to topographical technology we are seeing 5 percent correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimize iterations while meeting our design goals in shorter timeframes."

To alleviate today's immense time-to-market pressures, Design Compiler 2010 extends topographical technology to further optimize its links with IC Compiler, tightening correlation down to 5%. Additional physical optimization techniques are applied during synthesis, and physical guidance is created and passed to IC Compiler, streamlining the flow and speeding placement in IC Compiler by 1.5X. Design Compiler 2010 also provides RTL designers access to IC Compiler's floorplanning capabilities from within the synthesis environment. With the push of a button, designers can perform what-if floorplan exploration, enabling them to identify and fix floorplan issues early and achieve faster design convergence.

"For the last few years, we have used Design Compiler's Topographical technology to find and fix design issues during synthesis to give us predictable implementation," said Shih-Arn Hwang, Deputy Director R&D Center at Realtek. "We see Design Compiler 2010 synthesis results closely correlating to physical results, while accelerating placement in IC Compiler by 1.5X. This tight correlation between synthesis and layout, along with faster runtimes, is exactly what we need for reducing iterations and significantly shortening design schedules in 65 nanometer and smaller process technologies."

Design Compiler 2010 includes a new, scalable infrastructure designed to deliver significant runtime speed-up on multicore compute servers. It employs an optimized scheme of distributed and multithreaded parallelization techniques, delivering an average of 2X faster runtime on quad-core compute servers while achieving zero deviation of the synthesis results.

"We've focused Design Compiler improvements on helping designers shorten design cycles and improve productivity," said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group. "Since the introduction of topographical technology, the impact of logic synthesis on accelerating design closure with physical implementation has grown significantly. Design Compiler 2010 continues this trend, delivering a significant decrease in iterations and reducing run times in physical implementation. We have achieved this while dramatically updating our software infrastructure to best utilize the latest microprocessor architectures."