Showing posts from April, 2010

Acceleration And Emulation – Why HW/SW Integration Needs Both

Nokia N8 is official: Priced €370 ($494)

Cadence Debuts Verification Computing Platform

Gawker Media received no direct revenue from iPhone 4G scoop

Google Acquires iPad Chip Maker Startup Agnilux

Lost iPhone Reveals Hardware Improvements

Achieving Fiber-Optic Speeds over Copper Lines

PCI Express-based MicroTCA Design Options

Driving Flexibility into Automotive Electronics Design

SuperSpeed Your SoCs with USB 3.0 IP

Advertisement: HP Coupons & Coupon Codes

Improving I/O Virtualization Performance with PCI Express

A Cost Effective Way to Design Next Generation Communications Infrastructure Equipment

Stay in control of schedules and costs when requirements change

At-Speed and Advanced Fault Models for Achieving High Quality Test

SDRAM Memory Systems: Architecture Overview and Design Verification

Protect Your FPGA Against Piracy: Cost-Effective Authentication Scheme Protects IP in SRAM-Based FPGA Designs

Restrictive Design Rules and Their Impact on 22nm Design and Physical Verification

Useful links for Electronics Hobbyists

A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration

10 questions to ask when choosing a virtualization solution

Infineon India Walk-in Interviews (17 April 2010, Saturday)

List of VLSI and related Conferences

Post a Job on The Digital Electronics Blog

Pain Killers for the Fixed-Point Design Flow

High level analysis of false paths

Words of wisdom

Words of wisdom

MIPI & SoC Integration Lunch & Learn Seminar

Advanced On-Chip Variation (OCV) in PrimeTime

Memory Management Technique Speeds Apps By 20%

Enabling Rapid, Reliable Deployment of IP into System Designs

Words of wisdom

Words of wisdom

Verilog2C++

Splint Annotation-Assisted Lightweight Static Checking

Source Navigator for Verilog

Comit-TX Verilog Testbench Extractor

Incisive Conformal ASIC

System Architect for micro-architecture performance analysis and optimization during functional simulation

nECO for Verdi and Debussy debug systems

Functionally debug in RTL source using Identify RTL Debugger

Gatevision for Netlist debugging

Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route

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