Gatevision for Netlist debugging

GateVision  is a standalone graphical netlist analyzer that allows intuitive design navigation, schematic viewing, logic cone extraction, interactive logic cone viewing, and design documentation. GateVision's easy-to-read schematics and schematic fragments provide excellent debug support and accelerate the debug process.

Key Features:

   * On-the-fly schematic creation results in very high speed and capacity
   * Automatically extracts logic cones from user-defined reference points, and shows just the important portion of the circuit
   * Interactive logic cone navigation Allows compelling signal path tracing through the complete design hierarchy
   * Search-and-show capability allows easy location of specific objects shortens debug time
   * Design hierarchy browser provides easy navigation through the design hierarchy and gives compact hierarchy overview
   * Object cross-probing highlights selected objects in all design views (schematic, logic cone and HDL view) and shortens debug time
   * Context-sensitive menus and easy-to-use GUI
   * Verilog and EDIF netlist interface allows integration s into almost any design flow
   * Userware API allows addition of custom features

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