Verification
Verification and Testing
Verification: In order to verify the functional correctness of a design, one needs to capture the model of the behavior…
Testing
Load and stress testing.
One of the most common, but unfortunate misuse of terminology is treating "load testing" and "stress tes…
Metastability
Digital Logic Metastability Definitions
read further on.... http://www.interfacebus.com/Design_MetaStable.html
Timing
Max Frequency calculation
In the simplest form: FF1 - combo - FF2 ( this is how things look physically for our consideration) Tmin = Tclk2Q (F…
Timing
Ways to increase frequency of operation
Check critical path and optimize it. Add more timing constraints (over constrain). pipeline the architecture to the max…
Formal Verification
When are DFT and Formal verification used?
DFT: manufacturing defects like stuck at "0" or "1". test for set of rules followed during the init…
Gated clocks
Adv and DisAdv of Gated Clocks
Advantges: used to save power by masking the clock to the flops. used in clock switching circuits. Reduces routing burd…
Setup
Setup and Hold times
The setup time is the time the data inputs must be valid before the clock/strobe signal. tSU(chip-pin)= tSU(FF) - Tdela…
Wire load
Wire load models
Wire loading models contain all the information required by compile to estimate interconnect wiring delays. A typical W…
Why
Why interrupts are active low?
What interrupts are active low in digital circuits? In digital circuits, an interrupt is a signal that causes the proce…
Slack
Slack
slack is defined as the difference between the reqd_arrival time of a signal & it's actual arrival time. It sho…
Poleysilicon
Polysilicon Vs Metal
Normally polysilicon has more resistance compared to metal. For shorter distance we go with polysilicon keeping fabrica…
Nor
NAND or NOR design
NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three t…
FPGA
FPGA & ASIC based design
The main diferrence between ASIC and FPGA based design is in the Back-end. In FPGAs there is not much activities in bac…
False Path
Default paths and False paths
The path in digital circuits which is not associated with a clock, is known as default path. While considering and calc…
FPGA
Coarse and Fine grained architectures
Coarse-grained architectures consist of fairly large logic blocks, often containing two or more look-up tables and two …
RTL
Latch Vs Flip Flop
A latch and a flip-flop are two basic building blocks in digital electronics used to store binary data. The main differ…
RTL
Glitches, Hazards and Lizards
A glitch is a momentary error condition on the output of a circuit due to unequal path delays in a circuit. It is seen …
Synthesis
Low power design
Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate …
Interview Questions
Verilog Awareness - Interview Questions
Q: Given the following Verilog code, what value of "a" is "displayed"? always @(clk) begin a = …