Nor
Why NAND gates are preferred over NOR gates?
NAND and NOR gates are universal logic gates, which means any Boolean expression can be implemented without using any o…
Pipelining
Comp Arch - Pipelining
Pipelining is an implementation technique where multiple instructions are overlapped in execution. It not decrease the …
Hazards
Logic Hazards
Some basics before we head further... Steady State Behaviour: Value of o/p after the i/p's have been steady for som…
PLL
Delay Locked Loop (DLL)
Why not a PLL: PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both hi…
PLL
Phase locked loop (PLL)
PLL stands for 'Phase-Locked Loop' and is basically a closed loop frequency control system, whose functioning …
Interview Questions
Fifo depth calculation
A First-In-First-Out (FIFO) depth calculation is a crucial aspect of designing and implementing FIFO buffers or queuing…