Interview Questions
Synthesizable Verilog from behavioral constructs - 4
When implementing Verilog tasks in modules, the best approach is to group tasks that have the same output signals into …
Interview Questions
synthesizable Verilog from behavioral constructs - 3
To modify a behavioural Verilog fork and join statement to make it synthesizable. Behavioural: command1; fork //…
Interview Questions
synthesizable Verilog from behavioral constructs - 2
Modifying a behavioural Verilog while statement to make it synthesizable. Behavioural: command1; while (x != 0) …
Interview Questions
synthesizable Verilog from behavioral constructs - 1
Modifying a behavioural Verilog wait statement to make it synthesizable. Behavioural: command1; wait (x != 0); c…
Digital
A nice site for basics on Digital Logic Design
http://www.allaboutcircuits.com/ , Look up Volume IV - Digital Summary of topics covered... Chapter 1: NUMERATION SYS…
Learning
1's complement and 2's complement
In digital logic design, one of the ways to represent negative numbers is by using signed number representation. One of…
Setup
negative setup and hold time
A negative setup and hold condition is a very interesting proposition in static timing analysis. Support for this type …
I2C
I2C Questions
Question: What is the maximum distance of the I2C bus? This depends on the load of the bu s and the speed y…
Interview Questions
more questions
1. Given 2 4 bit nos, A= 1001, b= 1100 HOW DO YOU ExOR THEM using minimum number of gates? how do you nand them? …
Xor
Mux out of an XOR
Here is some background and a step to solve the problem: A set of {+, . , '} is functionally complete because every…
RTL Design
Design Interview questions
1.) You are adding 8 10-bit numbers. How many bits do you need for the result? 2.) You are adding two 2's-compleme…
Glitch
Glitch in a combinational circuit and the way to avoid that.
A glitch resistive transition means, it is not possible to have any intermediate momentary values during output transit…
For Loop
Why "FOR LOOP" is not advisable
Why "FOR LOOP" is not advisable to code in RTL eventhough it is synthesizable? I agree with this explanation.…
Setup
Setup Time & Hold Time - By popular demand
a) Generally speaking SETUP fixing is always DIFFICULT. This can be resolved by inserting buffers (as you mentioned) on…
Logic Density
Logic Density
Find the resource elements consumed during design stage that is before RTL coding.Is it necessarily needed to draw the …
Negative hold time
Negative hold time
Negative hold time is generally seen where a delay is already added in the data path inside the flop. This is usually d…
TOC
Test
Category Name ~^~123~^~ ~^~123~^~ | ~^~123~^~ ~^~123~^~ ~^~123~^~ | ~^~123~^~ ~^~123~^~ ~^~123~^~ | ~^~123~^…
Nor
Why NAND gates are preferred over NOR gates?
NAND and NOR gates are universal logic gates, which means any Boolean expression can be implemented without using any o…
Pipelining
Comp Arch - Pipelining
Pipelining is an implementation technique where multiple instructions are overlapped in execution. It not decrease the …
Hazards
Logic Hazards
Some basics before we head further... Steady State Behaviour: Value of o/p after the i/p's have been steady for som…