Asynchronous in a synchronous world - Introduction
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article…
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article…
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + dat…
module shifter (result, value_in, direction, type, length); output [7:0] result; input [7:0] value_in; input direction;…
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which i…
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between bl…
Clock jitter is the deviation from the ideal timing of clock transition events. Because such deviation can be detriment…
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little…
Basics of Clock Tree Synthesis: The main idea is to balance the skew between endpoints. They are built with the followi…
..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amoun…
"Safe" State Machines: If the number of states (N) is a power of 2 and you use a binary or gray-code encoding…
Metastability in electronic circuits Metastability is a phenomenon that occurs in digital circuits when an input signal…
Delay statements, e.g. @(posedge clock), require careful attention if there are several in a row. If there are only del…
When implementing Verilog tasks in modules, the best approach is to group tasks that have the same output signals into …
To modify a behavioural Verilog fork and join statement to make it synthesizable. Behavioural: command1; fork //…
Modifying a behavioural Verilog while statement to make it synthesizable. Behavioural: command1; while (x != 0) …
Modifying a behavioural Verilog wait statement to make it synthesizable. Behavioural: command1; wait (x != 0); c…
http://www.allaboutcircuits.com/ , Look up Volume IV - Digital Summary of topics covered... Chapter 1: NUMERATION SYS…
In digital logic design, one of the ways to represent negative numbers is by using signed number representation. One of…
A negative setup and hold condition is a very interesting proposition in static timing analysis. Support for this type …
Question: What is the maximum distance of the I2C bus? This depends on the load of the bu s and the speed y…