ARP Q&A
What is ARP? Address Resolution Protocol (ARP) is a network protocol, which maps a network layer protocol address to a …
What is ARP? Address Resolution Protocol (ARP) is a network protocol, which maps a network layer protocol address to a …
What is Ethernet? Ethernet is a Local Area Network (LAN) cabling and signaling specification for baseband networks. Eth…
For designs with significant control flow, algorithms can be described in software languages, flowcharts, abstract stat…
The phrases "behavioural model" and "structural model" are commonly used for what we'll call &q…
Requirements Description of what the customer wants Algorithm Functional description of computation. Probably not synth…
Based on past experience i had with FPGAs... Flip-flops are almost free in FPGAs, the reason is that in FPGAs, the area…
Performing static timing analysis is the process of verifying that every signal path in a design meets required clock-c…
The purpose of synchronizing signals is to protect downstream logic from the metastable state of the first flip-flop in…
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article…
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + dat…
module shifter (result, value_in, direction, type, length); output [7:0] result; input [7:0] value_in; input direction;…
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which i…
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between bl…
Clock jitter is the deviation from the ideal timing of clock transition events. Because such deviation can be detriment…
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little…
Basics of Clock Tree Synthesis: The main idea is to balance the skew between endpoints. They are built with the followi…
..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amoun…
"Safe" State Machines: If the number of states (N) is a power of 2 and you use a binary or gray-code encoding…
Metastability in electronic circuits Metastability is a phenomenon that occurs in digital circuits when an input signal…
Delay statements, e.g. @(posedge clock), require careful attention if there are several in a row. If there are only del…
When implementing Verilog tasks in modules, the best approach is to group tasks that have the same output signals into …
To modify a behavioural Verilog fork and join statement to make it synthesizable. Behavioural: command1; fork //…
Modifying a behavioural Verilog while statement to make it synthesizable. Behavioural: command1; while (x != 0) …