Synthesis

Logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (…

Comprehensive Verilog Tutorials - Introduction

The history of the Verilog HDL goes back to the 1980s, when Gateway Design Automation developed Verilog-XL logic simula…

Comprehensive Verilog Tutorials - Welcome

This is an Introductory & Comprehensive Verilog Course, which covers.. Modeling Designs for Digital Simulation. Mod…

Sponsors

Be a sponsor & Support this Blog Some of our Proud Sponsors: VLSIChipDesign Checkout how much a Text-Link is worth …

Invitation to be a contributor on this blog!

We are happy to invite you as a contributor to this blog in digital electronics. Of course, you can choose to be anonym…

Added Features!

After much awaited delay due to developments on the blogger in beta, i m happy to announce that i have successfully con…

Gate level simulation - Introduction

Gate level simulation (GLS) is a technique for verifying the functionality and timing of a digital circuit after it has…

RTL considerations and Functional verification of low power designs

This article is about RTL in a Multi-Voltage environment and it's implication on verification. In the earlier …

Todays Low Power Techniques

Lets take a look at the various low power techniques in use today. I would classify them into 2 categories Structu…

Design Elements of Low Power Design

Special cells are required for implementing a Multi-Voltage design. Level Shifter Isolation Cell Enable Level Shifter…

Infrastructure Needs for Multi-Voltage Designs

Before we start looking at implementing a Multi-Voltage design there are certain questions that need to be answered to …

Multi Voltage magic

In the last few weeks i have been quite busy with a lot of research on low power design. There are so many tutorial…

Vt Cells and Spacing Requirements

Multi-Vt placement/spacing concerns I was just thinking about most common concerns faced today in addressing leakage p…

Free verilog simulator

http://www.logicsim.com/

Event simulation versus cycle simulation

By popular demand: Event simulation allows the design to contain simple timing information - the delay needed for a sig…

Updates

Last 2 weeks has witnessed a sudden surge in visitors and so i decided to continue my experiments for some more time wi…

NOTICE

I have found that this Blog has not attracted enough enthusiasts as expected. So due to lack of participation i m force…

basic arithmetic

What are the representations for, zero in 2's compliment the most positive integer that can be represented using…

Testing

You get the final chip back from the FAB. Now you do the smoke test(power up). Hopefully assuming that things are well …

Significance of contamination delay in sequential circuit timing

Q: What is the significance of contamination delay in sequential circuit timing? Fact: 70-80% of designers who deal …

FSM based Interview Question

Calculate the size of the ROM if the sequential element is 'n' bits wide. What is the number o…

Approaches that can ease multi-clock designs

Problem 1: Metastability Solution: Use appropriate synchronizers. (please read my earlier articles to understand the …

Key points in Logic Design Timing

In a synchronous design, all memory elements, flip-flops and latches, are synchronized be a master clock. A timing di…

FSM Questions

Design an FSM that has 1 i/p and 1 o/p. The o/p becomes 1 and remains 1 when at least two 0's and two 1's have …

Verilog Question

A 3:1 mux has three data inputs D0, D1 and D2, two select inputs S0 and S1 and one data output Y. The value of output…

sequential circuits

In order for the circuit shown above to operate correctly what constraints on tH and tS are necessary? Express…

sequential circuit

Assuming that the clock period is 25ns, what is the maximum setup time for the registers for which this …

sequential circuit

What is the smallest value for the ROM's contamination delay that ensures the necessary timing spec…

sequential circuit

What is the smallest clock period for which the circuit still operates correctly? By removing the pair of i…

sequential circuit

Calculate timing parameters for the system as a whole taking into account d1 and d2. Don't make any assumption abou…

sequential circuit

Calculate the timing parameters (tS, tH, tCD, tPD, tCLK) for this system as a whole.

TCP Q&A

What is TCP? Transmission Control Protocol ( TCP ) provides a reliable byte-stream transfer service between two endpoin…

IP Fragmentation Q&A

What is meant by IP fragmentation? The breaking up of a single IP datagram into two or more IP datagrams of smaller siz…

IP Addressing Q&A

RARP Q&A

What is RARP? Reverse Address Resolution Protocol (RARP) is a network protocol used to resolve a data link layer addres…

ARP Q&A

What is ARP? Address Resolution Protocol (ARP) is a network protocol, which maps a network layer protocol address to a …