VHDL Coding Guidelines
HDL Coding Guidelines - Part 5
Critical Policies to Keep note! Balance clock to delta accuracy Pull-ups and pull-downs have to be modeled on chip leve…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 4
To Avoid common Errors A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 3
Portability Language for modeling should be VHDL-87 VHDL-93 keywords should not be used Verilog keywords should not be…
IFIP/IEEE VLSI-SoC 2008 International Conference, 16th International Conference on Very Large Scale Integration
IFIP/IEEE VLSI-SoC 2008 International Conference 16th International Conference on Very Large Scale Integration Oct…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 2
When Compiling (VHDL): A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 1
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It…
Case analysis
What is case analysis?
Case analysis lets you perform timing analysis using logic constants or logic transitions on ports or pins to limit the…
Timing
Register re-timing
Register retiming is a sequential optimization technique that moves registers through the combinational logic gates of …
Soft Macro
Soft Macro Vs Hard Macro?
Last updated: 26th August 2023 Total Views: 22378 In this blog post, we will compare and contrast two types of macros …
Delays
Delays in ASIC/VLSI design
Source Delay/Latency, Network Delay/Latency, Insertion Delay, Transition Delay/Slew, Path Delay, Net delay, Wire delay,…
Interview Questions
Latch based Interview Question
Latch-based designs are sometimes used for high-speed digital circuits. One possible configuration places combinational…
Interview Questions
NVIDIA Interview Question
Two stages are added to the pipeline discussed in the earlier post to form the circuit shown below. 1. …
Interview Questions
NVIDIA Interview Question
Your task is to develop a method to reduce the power consumption of the 2-stage image processing pipeline shown below (…
Interview Questions
NVIDIA Interview Question
Circuit below, which implements operation C, has been designed such that it has two modules i and j, with the delays sh…
Interview Questions
NVIDIA Interview Questions
You are designing a circuit that implements two operations A and B as shown below. NOTES: 1. At any poi…
Interview Questions
NVIDIA Interview Questions
State whether each of the following statements is True or False . Justify your answers. RTL simulation is faster th…
skew
Useful Skew - Using Clock Skew as a Tool to Achieve Optimal Timing
What is Useful Skew anyway? Some nonzero skews can become useful by creating safety margins to guard against delay vari…
Interview Questions
Pipelining Interview Question
Pipe-lining is particular form of re timing where the goal is to increase the throughput (number of results per second…
Interview Questions
Logic Design Interview Question
In thinking about the propagation delay of a ripple-carry adder, we see that the higher-order bits are "waiting&q…
Interview Questions
CMOS Interview Question
Occasionally you will come across a CMOS circuit where the complementary nature of the n-channel pull-downs and p-chan…
Interview Questions
Logic Design Interview Question
A priority encoder has inputs that are assigned in some predetermined order. The output is the binary encoding of the …
Interview Questions
STA Interview Question
Suppose we are building circuits using only the following three components: inverter: tcd = 0.5ns, tpd = 1.0ns, tr = …
Interview Questions
STA Interview Question
Suppose that each component in the circuit below has a propagation delay (tpd) of 10ns, a contamination delay (tcd) of…
Interview Questions
Discussion based Interview Question
Your company, EarGuard Inc., is working on the q-pod, a new music player. The chief verification engineer has just rep…
Interview Questions
Interview Question
You are on the committee to define a uniquely Indian Hardware Description Language: IndieHDL — a cool language from a …