Event Driven Simulation
Event driven simulation/simulator
A latch or flip-flop does not always respond to activity on its inputs. If an enable or clock is inactive, changes at t…
Linting
Linting tools
Some of the tools used for design verification of ICs have their roots in software testing. Tools for software testing …
White box testing
White box testing or Black box testing
When performing verification, the target device can be viewed as a white box or a black box. During whitebox testing, d…
Netlist
Formal Verification or EquivalenceChecking
Design verification, must show that the design, expressed at the RTL or structural level, implements the operations des…
Interview Questions
Avago Technologies (former HP group) Interview Questions
How do you minimize clock skew/ balance clock tree? Given 11 minterms and asked to derive the logic function. Given C…
Interview Questions
Hynix Semiconductor Interview Questions
How do you optimize power at various stages in the physical design flow? Power optimization is an important aspect of p…
Interview Questions
Hughes Networks Interview Questions
What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations? Explai…
Qualcomm
Qualcomm Interview Questions
RTL Design In work Design Verification In work Physical Design In building the timing constraints, do you need to const…
Interview Questions
Texas Instruments (TI) Interview Questions
How are timing constraints developed? Explain timing closure flow/methodology/issues/fixes. Explain SDF (Standard Del…
Interview Questions
ST Microelectronics - Interview Questions
What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)? What was the a…
Interview Questions
Digital design interview questions
Search in this blog for all the available articles and resources! ------------------------------- PROMOTION --------…
Technical Leadership
The Great Divide – Technical Leadership and Project Management
[Via Coaching Excellence in IC Design Teams] This is bitterly true. Intel is one example of why it is #1.
Debates and Discussions
47 CEOs for Cadence
[Via Deepchip ] I feel even that baiting a big name CEO from EDA background, from the list will not help. This is more …
what will work
Unit delay simulation - an intermediate step in Gate level simulation!
This is an intermediate step during Gate level simulation! Unit delay simulation operates on the assumption that all th…
what will work
Different types of simulations!
Functional simulation : Simulation of a design description. This is also called spec simulation or concept simulation. …
Search
Get your Blog listed in our Google Custom Search Engine
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Self Esteem
Performance-Contingent Self Esteem
Don't be too committed in your profession where you reach a point where it might boomerang, leaving you depressed, …
Terrorism
Mumbai Terror!
If you want to get in touch with your loved one in Mumbai... follow this link http://mumbaiterrorhelpline.blogspot.com/…
Interview Questions
Digital Logic Design - Interview Essentials!
Hello Readers, Due to the recent spate of Layoffs , a high amount of panic and interview preparation frenzy has seeped…
VLSI
What Users Would Change About This Blog!
The best part about this survey is that you get to see what users are looking for, whats bothering them that they would…