I have something to explain
The Economics of Test, Part - I
What are the factors that influence the cost of test? Quality and test costs are related, but they are not inverse of o…
TCL for EDA
TCL for EDA - A repository Free TCL/TK tools, scripts for EDA...
http://www.tclforeda.org/ The TCL for EDA project is an open-source repository of TCL/TK tools, applications, scripts a…
Transport Delay
Transport delay / Inertial Delay / Delta Delay
In Verilog and VHDL, there are three types of delays that are commonly used in digital logic simulation: delta delay,…
Cycle Simulation
Cycle based simulation
New design starts continue to grow in gate count, and the amount of CPU time required to simulate these designs tends t…
Event Driven Simulation
Event driven simulation/simulator
A latch or flip-flop does not always respond to activity on its inputs. If an enable or clock is inactive, changes at t…
Linting
Linting tools
Some of the tools used for design verification of ICs have their roots in software testing. Tools for software testing …
White box testing
White box testing or Black box testing
When performing verification, the target device can be viewed as a white box or a black box. During whitebox testing, d…
Netlist
Formal Verification or EquivalenceChecking
Design verification, must show that the design, expressed at the RTL or structural level, implements the operations des…
Interview Questions
Avago Technologies (former HP group) Interview Questions
How do you minimize clock skew/ balance clock tree? Given 11 minterms and asked to derive the logic function. Given C…
Interview Questions
Hynix Semiconductor Interview Questions
How do you optimize power at various stages in the physical design flow? Power optimization is an important aspect of p…
Interview Questions
Hughes Networks Interview Questions
What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations? Explai…
Qualcomm
Qualcomm Interview Questions
RTL Design In work Design Verification In work Physical Design In building the timing constraints, do you need to const…
Interview Questions
Texas Instruments (TI) Interview Questions
How are timing constraints developed? Explain timing closure flow/methodology/issues/fixes. Explain SDF (Standard Del…
Interview Questions
ST Microelectronics - Interview Questions
What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)? What was the a…
Interview Questions
Digital design interview questions
Search in this blog for all the available articles and resources! ------------------------------- PROMOTION --------…
Technical Leadership
The Great Divide – Technical Leadership and Project Management
[Via Coaching Excellence in IC Design Teams] This is bitterly true. Intel is one example of why it is #1.
Debates and Discussions
47 CEOs for Cadence
[Via Deepchip ] I feel even that baiting a big name CEO from EDA background, from the list will not help. This is more …
what will work
Unit delay simulation - an intermediate step in Gate level simulation!
This is an intermediate step during Gate level simulation! Unit delay simulation operates on the assumption that all th…
what will work
Different types of simulations!
Functional simulation : Simulation of a design description. This is also called spec simulation or concept simulation. …
Search
Get your Blog listed in our Google Custom Search Engine
To get your Blog listed in our Google Custom Search Engine please send us an e-mail with your Blog details to onenanome…
Self Esteem
Performance-Contingent Self Esteem
Don't be too committed in your profession where you reach a point where it might boomerang, leaving you depressed, …
Terrorism
Mumbai Terror!
If you want to get in touch with your loved one in Mumbai... follow this link http://mumbaiterrorhelpline.blogspot.com/…
Interview Questions
Digital Logic Design - Interview Essentials!
Hello Readers, Due to the recent spate of Layoffs , a high amount of panic and interview preparation frenzy has seeped…
VLSI
What Users Would Change About This Blog!
The best part about this survey is that you get to see what users are looking for, whats bothering them that they would…
VLSI Conference
Layoff Watch!
Announced Worldwide Layoffs As of 30th January 2009 Infineon - 3000 Qimonda - 3000 (Bankrupt: 23 Jan 09) Renesas -…
Investments
Intel will invest through recession!
Intel will continue to invest in products and technologies even though it sees that a U.S.financial meltdown is likely …
Wireless
10 Gbps Wireless
Engineers at Battelle have come up with a way to send data through the air at 10 Gigabits per second using point-to-po…
Questions
VLSI Blogs
Based on the content and articles in this blog do you really think that this blog should be categorized under VLSI or A…
Links
How to get a free link to your ASIC or VLSI Blog?
This is how you can get a free link to your blog. If you are not already a member of the ASIC/VLSI/Digital Electronics …
Forecats
Semiconductor forecast looks grim!
According to IC insights , the maket forecast looks grim for 2008 total worldwide IC market growth, noting shrinking de…
XVGA
Simple XVGA (1024x768) Controller in Verilog
module xvga(clk,hcount,vcount,hsync,vsync); input clk; // 64.8 Mhz output [10:0] hcount; output [9:0] vcount; …
References
Coaching Excellence in IC Design Teams: Why Can't we get Rid of that Thorn in our Process?
Coaching Excellence in IC Design Teams: Why Can't we get Rid of that Thorn in our Process? Commenting on this artic…
Jobs
Invitation to Freshers!
Infineon India - Bangalore is planning for a Fresher's Event in September 08 & thereby invites CVs of friends w…
Interview Questions
VLSI Interview Questions
One day you are strolling the hallways in search of inspiration, when you bump into a person from the marketing departm…
Interview Questions
Digital Design Interview Questions
Your task is to do the power analysis for a circuit that should send out a one-clock-cycle pulse once every 16 clock cy…
Interview Questions
Interview Question
Your manager has given you the task of implementing the following pseudo code in an FPGA: if is_odd(a + d) { p = (a +…
Verilog
Digital "Greatest Common Divisor (GCD)" - Euclid’s algorithm
Updated on 25th Jan 2022!! The Euclidean algorithm is a method for finding the greatest common divisor (GCD) of two or …
Verilog
Digital "Square root" Computation of a number
By Popular Demand! module sqrt (clk,data,start,answer,done); input clk,start; input [7:0] data; output [3:0] answer;…