Testing
The Economics of Test, Part - IV
Detecting a defective unit is often only part of the job. Another important aspect of test economics that must be consi…
Testing
The Economics of Test, Part - III
However, if devices are tested, feature sizes can be reduced and more die will fit on each wafer. Even after the die ar…
I have something to explain
The Economics of Test, Part - II
The table depicted shows test cost broken down into four categories some of which are one-time, non recurring costs whe…
I have something to explain
The Economics of Test, Part - I
What are the factors that influence the cost of test? Quality and test costs are related, but they are not inverse of o…
TCL for EDA
TCL for EDA - A repository Free TCL/TK tools, scripts for EDA...
http://www.tclforeda.org/ The TCL for EDA project is an open-source repository of TCL/TK tools, applications, scripts a…
Transport Delay
Transport delay / Inertial Delay / Delta Delay
In Verilog and VHDL, there are three types of delays that are commonly used in digital logic simulation: delta delay,…
Cycle Simulation
Cycle based simulation
New design starts continue to grow in gate count, and the amount of CPU time required to simulate these designs tends t…
Event Driven Simulation
Event driven simulation/simulator
A latch or flip-flop does not always respond to activity on its inputs. If an enable or clock is inactive, changes at t…
Linting
Linting tools
Some of the tools used for design verification of ICs have their roots in software testing. Tools for software testing …
White box testing
White box testing or Black box testing
When performing verification, the target device can be viewed as a white box or a black box. During whitebox testing, d…
Netlist
Formal Verification or EquivalenceChecking
Design verification, must show that the design, expressed at the RTL or structural level, implements the operations des…
Interview Questions
Avago Technologies (former HP group) Interview Questions
How do you minimize clock skew/ balance clock tree? Given 11 minterms and asked to derive the logic function. Given C…
Interview Questions
Hynix Semiconductor Interview Questions
How do you optimize power at various stages in the physical design flow? Power optimization is an important aspect of p…
Interview Questions
Hughes Networks Interview Questions
What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations? Explai…
Qualcomm
Qualcomm Interview Questions
RTL Design In work Design Verification In work Physical Design In building the timing constraints, do you need to const…
Interview Questions
Texas Instruments (TI) Interview Questions
How are timing constraints developed? Explain timing closure flow/methodology/issues/fixes. Explain SDF (Standard Del…
Interview Questions
ST Microelectronics - Interview Questions
What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)? What was the a…
Interview Questions
Digital design interview questions
Search in this blog for all the available articles and resources! ------------------------------- PROMOTION --------…
Technical Leadership
The Great Divide – Technical Leadership and Project Management
[Via Coaching Excellence in IC Design Teams] This is bitterly true. Intel is one example of why it is #1.
Debates and Discussions
47 CEOs for Cadence
[Via Deepchip ] I feel even that baiting a big name CEO from EDA background, from the list will not help. This is more …