A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integra…
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integra…
The following is a list of conferences specific to the VLSI industry. It was earlier part of a widget on the sidebar bu…
Now you can post a job on this blog for as low as $15/Week or $30/Month ! This blog receives approx 25,000 page views …
Taking a floating-point representation of an algorithm into a fixed-point representation is an integral step on the pat…
Sometimes the delay through a component is dependent upon the values on signals. This is because different paths in the…
Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is des…
This application note from synopsys describes the advanced on-chip variation (OCV) solution in PrimeTime, including th…
A paper (PDF) to be presented later this month at the IEEE International Parallel and Distributed Processing Symposi…
This webcast highlights The SPIRIT Consortium's new IP-XACT 1.4 specification which expands the range of IP that c…
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-ac…
Splint is a tool for statically checking C programs for security vulnerabilities and coding mistakes. With minimal e…
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog…
Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench.…
With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It…
nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug syst…
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware direc…
Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementati…
Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, pro…
Based on the competency level of the applicants we reserve the right to offer a free service or charge a minimum admini…
The semiconductor industry is struggling to maintain its momentum down the path of Moore’s Law, and it is becoming clea…
VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment …
VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN…
The articles, publications and shared documents are included in this blog by the contributing authors as a mechanism t…
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
Cell phone radiation. Some consider it a heath-hazard of paramount importance. Others couldn't care less. Whichever…