VLSI
VSIDE - VSDSP Integrated Development Environment
VLSI Solution has announced VSIDE - the Integrated Development Environment for VSDSP Processor Family. VSIDE is an inte…
VHDL
VLSI/ASIC/VHDL Interview Questions
1. **For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the p…
Information
Information
In a couple of weeks time the current blog @ http://digitalelectronics.blogspot.com will be hosted on a dedicated doma…
Press Release
Press Release: Baolab creates nanoscale MEMS inside the CMOS wafer
Baolab Microsystems has announced a new technology to construct nanoscale MEMS (Micro Electro Mechanical Systems) withi…
Grid
Grid Computing Vs Cluster Computing
A cluster computer is a set of CPU nodes that are used to solve any problem over a network. The way in which this coope…
Verification
Acceleration And Emulation – Why HW/SW Integration Needs Both
Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play.…
Nokia
Nokia N8 is official: Priced €370 ($494)
Nokia's N8 is now official would see a launch during April. With a packed design that includes a 12 megapixel came…
Verification
Cadence Debuts Verification Computing Platform
Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called …
News
Gawker Media received no direct revenue from iPhone 4G scoop
In response to the iPhone 4g post i ran yesterday i got quite a few comments and i want to highlight one of them specif…
iPad
Google Acquires iPad Chip Maker Startup Agnilux
" Google has purchased Agnilux , a secretive chip house made up of engineers who architected the heart of the iP…
Technology Review
Achieving Fiber-Optic Speeds over Copper Lines
A 100-year-old networking trick could boost transmissions over telephone infrastructure. Alcatel-Lucent has developed …
TechOnline
PCI Express-based MicroTCA Design Options
PCI Express-based MicroTCA platforms are generating more and more interest. This paper describes how small and cost-e…
White Papers
Driving Flexibility into Automotive Electronics Design
With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation aut…
White Papers
SuperSpeed Your SoCs with USB 3.0 IP
Since the introduction of the original USB standard in 1996, the USB interface has become one of the most successful c…
HP
Advertisement: HP Coupons & Coupon Codes
HP Home is the official HP website for personal computers, printing and imaging, servers and storage products for cons…
Virtualization
Improving I/O Virtualization Performance with PCI Express
Virtualization technology has been used in high-end servers for quite some time. The evolution of virtualization has b…
White Papers
A Cost Effective Way to Design Next Generation Communications Infrastructure Equipment
This white paper introduces a new category of programmable logic devices, the Tabula ABAX family based on Spacetime a…
TechOnline
Stay in control of schedules and costs when requirements change
Organizations need to know how changing requirements in a complex system will affect development. An effective change …
Testing
At-Speed and Advanced Fault Models for Achieving High Quality Test
With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed tes…
Verification
SDRAM Memory Systems: Architecture Overview and Design Verification
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is …
TechOnline
Protect Your FPGA Against Piracy: Cost-Effective Authentication Scheme Protects IP in SRAM-Based FPGA Designs
This application note describes FPGAs (field-programmable gate arrays) and how they can hold the key functions and th…
TechOnline
Restrictive Design Rules and Their Impact on 22nm Design and Physical Verification
Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, an…
VHDL
A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integra…
VLSI Conference
List of VLSI and related Conferences
The following is a list of conferences specific to the VLSI industry. It was earlier part of a widget on the sidebar bu…
Jobs
Post a Job on The Digital Electronics Blog
Now you can post a job on this blog for as low as $15/Week or $30/Month ! This blog receives approx 25,000 page views …
Synopsys
Pain Killers for the Fixed-Point Design Flow
Taking a floating-point representation of an algorithm into a fixed-point representation is an integral step on the pat…
Timing
High level analysis of false paths
Sometimes the delay through a component is dependent upon the values on signals. This is because different paths in the…
WebCasts
MIPI & SoC Integration Lunch & Learn Seminar
Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is des…
Synopsys
Advanced On-Chip Variation (OCV) in PrimeTime
This application note from synopsys describes the advanced on-chip variation (OCV) solution in PrimeTime, including th…
Processors
Memory Management Technique Speeds Apps By 20%
A paper (PDF) to be presented later this month at the IEEE International Parallel and Distributed Processing Symposi…
Verification
Enabling Rapid, Reliable Deployment of IP into System Designs
This webcast highlights The SPIRIT Consortium's new IP-XACT 1.4 specification which expands the range of IP that c…
Verilog
Verilog2C++
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-ac…
EDA Tools
Splint Annotation-Assisted Lightweight Static Checking
Splint is a tool for statically checking C programs for security vulnerabilities and coding mistakes. With minimal e…
Verilog
Source Navigator for Verilog
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog…
Test bench
Comit-TX Verilog Testbench Extractor
Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench.…
EquivalenceChecking
Incisive Conformal ASIC
With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It&#…
Verdi
nECO for Verdi and Debussy debug systems
nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug syst…
RTL
Functionally debug in RTL source using Identify RTL Debugger
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware direc…
Synopsys
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route
Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementati…
Timing
Probabilistic Timing Analysis
Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, pro…
Services
VLSI Career counselling request form
Based on the competency level of the applicants we reserve the right to offer a free service or charge a minimum admini…
3D Design
3D Integrated circuits
The semiconductor industry is struggling to maintain its momentum down the path of Moore’s Law, and it is becoming clea…
VN-Cover
EDA Tools - VN-Cover Emulator Coverage Analysis for HW Emulation
VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment …
VN-Cover
EDA Tools - VN-Cover Coverage Analysis
VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN…
Disclaimer
Copyright notice - Please read
The articles, publications and shared documents are included in this blog by the contributing authors as a mechanism t…
Verilog
Verilog and Specman 'e' Interview Questions
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
Phones
20 Cell phones with highest radiation levels
Cell phone radiation. Some consider it a heath-hazard of paramount importance. Others couldn't care less. Whichever…
Technology
GM Develops Augmented Reality Windshield
The entire windshield is turned into a transparent display to highlighting landmarks, obstacles and road edges on the w…
Top 25
Top 25 Chip ranking for 2009
ISuppli's final global revenue ranking for the top 25 semiconductor suppliers in 2009, in millions of U.S. dollars…
SystemC
SystemC AMS – A New Proposal For Mixed-Signal Verification
With increasing analog and mixed-signal content on systems-on-chip, design teams are looking for faster ways to run sys…