Intel buys Infineon wireless

Intel buys Infineon wireless

As per the management email sent to Infineon employees this morning, Infineon and Intel have signed the contracts relat…

High-Level Synthesis Blue Book

High-Level Synthesis Blue Book

The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL…

High-def iPhone 4

This new model available in black or white from June 24 has an unchanged pricing at $199 for the 16GB model and $299 fo…

SNUG India 2010 Registrations Open

SNUG India 2010 Registrations Open

The conference schedule and the registration links can be found here . With a program that is focused on helping you de…

Clock network design

Clock network design

In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…

IR drop driven placement

IR drop driven placement

The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to …

Clock skew variation estimation

Clock skew variation estimation

Clock skew variation estimation is an important topic in the design and analysis of high-performance digital circuits. …

Impact of dummy fill on timing

Impact of dummy fill on timing

How can you quantify the impact of dummy fill on post-layout timing?  Dummy fill can be inserted into a layout using SO…

Investigation on timing analysis inaccuracies

Investigation on timing analysis inaccuracies

Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, ma…

Distributions in statistical timing

Distributions in statistical timing

How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final d…

Dynamic power supply

Dynamic power supply

Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage ac…

Clock tree theory

Clock tree theory

Constructing a zero-skew clock tree can be formulated as constructing a path-length balanced tree (assuming path delay …

Statistical clock tree design

Statistical clock tree design

Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a stat…

Clock driver input alignment

Clock driver input alignment

Modern clock networks include several drivers in which delays are affected by the timing of their input signal transiti…

Transistor level technology remapping

Transistor level technology remapping

This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. Thi…

Transistor sizing / multi-Vt design

Transistor sizing / multi-Vt design

This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further…

Process variation extraction

Process variation extraction

Process variation extraction needs to be design specific, and based on random field simulation, as mechanical engineeri…

Backend physical design Interview Questions

Backend physical design Interview Questions

Updated 28 Aug 2023: I have listed below a set of common interview questions asked mainly in interviews related to phys…

Insulting leadership practices

Insulting leadership practices

Here are five of the most insulting leadership practices , the ones that virtually guarantee a business will end up wi…

Ways to improve your Interview Skills

Ways to improve your Interview Skills

With so much useful advise and talented career experts out there with often differing opinions, you will most likely en…

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