Intel looks At Creating A ‘Sub-Atom’ Chip Out Of India, renews focus on affordable PCs


Praveen Vishakantaiah, president of Intel India, said one innovation in the area of frugal engineering could soon be in the market. "With HCL, we have launched a nettop with a battery backup in the power adaptor. It's a three hour backup that helps in areas that do not have continuous power supply. The innovation was in the adaptor; if we had done it in the nettop, it would have raised the cost significantly," he said.

The past decade has seen several attempts to mass market PCs through innovations like the Simputer, Classmate PC and a $100 portable computer under the one-laptop-perchild initiative, some of which had Intel's involvement. Vishakantaiah said some of these initiatives did not fully appreciate the complexities of the Indian market. "Broadband connection is a problem, so is reaching rural areas. Classmate PC has been a success in Latin America, with success in one country influencing others in the region to take it up. But in India, success in one area is no guarantee that others will want to do it," he said.

So, apart from efforts to bring breakthroughs in chip architecture to make them both
low cost and multi-functional, Intel India will be looking at triggering innovations around low-cost chips, like the battery backup in the power adaptor. "Besides, in India, we can't just provide a box and expect people to know what to do with it, like in mature markets. We have to provide content, we have to work with the teachers using the PCs to explain what's possible.We will have applications
preloaded on the system which are activated only when the buyer starts using them;
and they pay only for the time they use the app.We will work with our partners and the entire supply chain to do all of this," Vishakantaiah said.

The company's chief technology officer, Justin Rattner, who was in Bangalore last week, told TOI he's starting what he calls a "frugal engineering" effort at its India facility. "It's intended to bring high technology to these huge populations, to those whom our products for the most part do not touch today. And India seemed to be the perfect place to do that kind of work," he said.

Rattner said he expects early results from the 'rethinking' initiative a year from now."We will do a number of projects in this area and quickly weed out the ones that aren't going anywhere, and focus on one or two that look promising," he said.

More at this link from Times of India!

Intel India labs will focus on parallel computing


Intel dominates the business of PC processors. But as consumers shift increasingly to tablets and smartphones, the company is trying to quickly move to serve those devices. On a visit to Bangalore last week, Justin Rattner, CTO of Intel, talked exclusively to TOI on a range of issues, from the nature of work its Bangalore labs are being asked to do, to some really futuristic, almost sci-fi, stuff.

More at this link from Times of India!

Infineon Technologies India, Walkin Interviews - 11th Dec 2010, 9AM to 4PM


Checkout the attached flyer for more details.

Glitch-Free Frequency Shifting


Download this white paper from Silicon Labs to learn how to simplify your timing design using glitch-free frequency shifting. This solution addresses low-power design challenges and the complexity of generating a wide range of frequencies in consumer electronics applications including audio, video, computing or any application that requires multiple frequencies.

Four key strategies for enabling innovation in the age of smart


On a smarter planet, intelligence is infused into the products,systems and processes that comprise the modern world. These include the delivery of services; the development, manufacturing, buying and selling of physical goods; and the way people actually work and live. No where may this transformation be more evident than in the creation of smarter products.

Improving IC Design Productivity with an Integrated Hardware Configuration Management System


Like software teams, hardware design teams need configuration management systems. However, Software Configuration Management (SCM) systems do not meet all the demands of hardware design teams. This paper explains the drawbacks of traditional data sharing and collaboration techniques and how a Hardware Configuration Management (HCM) system integrated into the design flow can enhance collaboration, improve productivity and dramatically reduce the need for re-spins.

10 Reasons to Customize a Processor Core


There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you've considered using a processor that you can customize. This paper discusses 10 good reasons why you should consider customizing your core in your next SoC design.

Qualcomm, Ericsson demo LTE in India


Wireless Broadband Business Services, one of Qualcomm’s India LTE partners, and Ericsson said they achieved LTE TDD outdoor mobility at 2.3 GHz Tuesday (Nov. 30) in northwestern India. The demo is part of Qualcomm’s strategy to accelerate the deployment of LTE in concert with 3G to drive the growth of mobile broadband in India.Qualcomm said it expects to attract other 3G HSPA or EV-DO operators to its LTE network in order to comply with Indian government deployment requirements for the wireless spectrum. Once those requirements are met, it will exit the Indian joint venture.

2010 EE Times Global Salary and Opinion Survey


The average base salary among the North American engineers surveyed totaled just over $100,000; annual compensation, including bonuses and overtime pay, averaged $107,300, according to our findings. North American engineers also reported the highest job satisfaction (64 percent) among the respondents.In China and India (where base salaries for engineers in most cases remain far lower than in the other surveyed regions), bonus figures for Chinese engineers tracked those in North America and Europe, but India failed to keep pace. Only more experienced Indian engineers reported a greater percentage of bonus payments during the past year.
Read on..

ARM founder claims that company will “obliterate” Intel


Diwali wishes


We like to wish all our readers a very happy and a safe Diwali. May this festive season bring you loads of happiness and prosperity.

Broadcom buys femtocell chip maker


Femtocells are small, low power cellular base stations that extend coverage indoors where signals are weak. Broadcom Corp. has signed a definitive agreement to acquire Percello Ltd., a privately-held company that develops system-on-a-chip (SoC) solutions for femtocells, for $86 million in cash.

Five good, five bad signs for IC market


We are in the fourth quarter and the outlook is cloudy for the rest of 2010 and heading into 2011. Here are some good and bad signs for the electronics industry.

Understanding system-level energy-management techniques and test


Gina Bonini is the worldwide embedded-system technical-marketing manager for Tektronix. In this article she talks about Power dissipation, Bus energy dissipation, PCI-e low power mode, some power saving modes and low power DDR DRAM.

Intel opens China fab


Intel Corp. has begun operations within its first fab in China, according to Dow Jones. In 2007, Intel won approval to build a $2.5 billion, 300-mm wafer plant in northern China for chip sets. The plan called for the fab to be in the city of Dalian. The fab will produce 65-nm devices.

Intel is also expanding in the U.S. As reported, Intel recently confirmed speculation that it will build a new R&D wafer fab in Hillsboro, Ore., and upgrade other existing U.S. facilities for 22-nm production at a total investment of between $6 billion and $8 billion.

The investment will create 800 to 1,000 permanent high-tech jobs and 6,000 to 8,000 construction jobs, Intel (Santa Clara, Calif.) said. The new development fab in Oregon, to be known as D1X, is slated for R&D startup in 2013.

One analyst thinks the fab will be ''450-mm ready.'' [Via: EETimes]

GlobalFoundries tech park in trouble?


A New York state agency plans to take over a technology park that houses the new 300-mm fab owned by U.S. silicon foundry upstart GlobalFoundries Inc.

GlobalFoundries' wafer fab under construction in New York state, Fab 8, would run the 22-nm production and more advanced nodes. Construction for Fab 8 started in July of 2009. The fab will have 60,000 wafer starts per month once it goes into full production. Production is expected to go online in 2012.

''The Fab 8 project is on schedule and construction is progressing very smoothly. We just have some concerns about a few pieces of infrastructure that need to be delivered. The state and (Luther Forest) are working out the details and we are confident they will address our concerns,'' according to a spokesman for GlobalFoundries.[Via: EETimes]

Is Intel prepping up for 450mm wafer sizes?


Is Intel preparing to push the issue with regard to its desire to move to 450-mm wafer sizes? One analyst thinks so. While most equipment is nowhere near ready at this stage (development has been limited ), C.J. Muse, an analyst with Barclays Capital, thinks the No. 1 chipmaker could specify that its newly announced D1X development fab in Oregon will be 450-mm capable (meaning it can accommodate 450-mm processing when/if the equipment becomes available).

Considering that Intel, Samsung and TSMC have said in the past that they want to see 450-mm development fabs by 2012 (fat chance), Intel almost has no choice but to build D1X with enough space to accommodate 450-mm processing. While the chances of the tools being ready for 450-mm by that date are slim, Intel must at least plan for the contingency if the company wants to send the message to its equipment suppliers that it is serious about this. While the 450-mm ball is rolling to some extent (450-mm wafer specs are ready; handlers and interfaces may be also), the question is when the big gear like lithography, CVD, RTP, etch systems and others, will be ready. Don't be surprised to see Intel make a public statement about this fab being 450-mm capable as a way to turn up the heat and spur tool development by equipment vendors who have mostly been dragging their feet. [via: EETimes]

INDIA Seminar Series 2010 - Modern Design Processes


An exciting agenda has been developed by Altium that will highlight many of the challenges facing today's electronics industry as well as put forward a case for rethinking tools and strategies to better align design capabilities with your current needs

Topics of focus will include:

* Design Process Management
* Design Team collaboration
* Collaborative PCB Design
* Design Data Management
* Version Control
* Also preview exciting new technology coming soon in the latest release of Altium Designer.

Who should attend:
Electronics Engineers, Electronics Managers, Team Leaders, Electronics Designers, Technical Directors, Technical Managers

For more info, please contact:
Rajesh Sawant +91 9663466910

Tech Talk - The Bleeding Edge (Oracle India, Sun Microsystems BU)


Last week i was invited to a Tech Talk organized by Oracle India (Sun Microsystems BU). The title of the talk was "Tech Talk - The Bleeding Edge, Evade your challenges– A dive into critical issues affecting High-end bleeding edge Semiconductors designs and the development engineers face off". The speaker was Mr. Sridhar Vajapey, VP, Hardware Development (Sun Microsystems BU), Oracle Corporation Inc.

The talk was highly informative covering the aspects of Semiconductor process Technology and challenges affecting the lower technology nodes of 28nm. The speaker also provided some very good insight into Sparc processor development, thermal management in a data center and issues with recreating silicon failures. Mr. Sridhar captivated the audience with his detail oriented talk and also dedicated time for answering questions from the audience. What kept me wondering was, how a VP kept himself up to date with technical details, issues and facts of current technologies. By the way did you ever wonder what Cutting edge, Leading Edge and Bleeding edge refer to? Do you know what they really mean?

Infineon takes over LTE specialist "Blue Wonder"


Infineon's Wireless Solutions unit has been working together with the Dresden design house "Blue Wonder" on the development of LTE technologies for one and a half years. Now Infineon has taken over the Saxony-based company together with its 50 employees.

Blue Wonder describes itself as a design house for LTE-IP and mobile communications
solutions serving the telecommunications and semiconductor industries. Blue Wonder’s team is made up of highly qualified specialists for mobile communications
solutions.

The core competencies encompass mobile broadband modem design and OFDMbased system development. First and foremost, the company’s special know-how in LTE Layer 1 supplements and complements the LTE development work of WLS and hence in future of Intel Mobile Communications.

The 4G mobile standard Long Term Evolution (LTE) is the successor of today’s 3G
standard UMTS/HSPA. It provides peak data rates of 150 Mbit/s downlink and 50
Mbit/s uplink. The perfor-mance in surfing the internet, playing online games and in
video telephony is as if the mobile devices were connected via DSL to the fixed
network.

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Digital systems engineering and perspectives on chip design


Today we are in the age of Digital Convergence seeing a major change in the way digital electronics systems are designed. Examples of such convergence can be seen in Microsoft's Xbox (From IT/Games to Home Entertainment), Apple's iPhone (From IT to Telecommunication/Entertainment), and Sony's Vaio (From Consumer Electronics to IT). This innovative look at technology has redefined road maps and business objectives of major corporations.

The title of this post is in fact a web-page created by us to highlight and educate folks in the semiconductor industry about the transformations that are happening in the way we try to design electronics and semiconductors. Our motivation is to avoid repetitions of many disasters we encounter in our interactions with the industry. We intend to highlight key aspects like design in HDL's, using HVL's and their importance, Importance of scripting languages and design automation and many other things.

Libelium opens the new ‘kitchen’ for electronics enthusiasts


Hardware design specialist Libelium opens a new community site for electronics enthusiasts offering a wide range of tutorials, cost-effective products, news, customer service and user-created hacks & recipes.

Libelium, a leading wireless and electronics innovator, announces the launch of the Cooking Hacks website. Drawing on the similarity between cooks exchanging recipes and engineers sharing hacks, the new website offers a wide range of fun resources for anyone keen on trying out electronics (and cooking). The website offers an affordable range of easy-to-use boards, modules and software downloads. It also offers tutorials and community facilities for sharing hacks and recipes. The site aims to make building electronic systems as straightforward as trying out recipes in the kitchen.

For more company information call +34 976 54 74 92 or visit http://www.libelium.com

Video review of the OpenPICUS first Webserver application


In march we had an article covering the Italian project made to fill the gap between Embedded Low Cost and Wireless. Today we have the first video review! Check it out.

Peer code review of RTL, Test bench, Test Cases for 100% Verification closure


The topic of "peer code review" is a widely discussed topic in the context of design verification. I remember the times very early in my career when my code was reviewed. There were lots of positives occasionally with some negatives which i have improved over time. What is that people look for in a code review and what is the value add? Is it the most easy and powerful way of hunting down issues and avoid reproducing them by educating people, that is too often neglected in favor of complex tools and methodologies which are never idiot-proof?

I still remember the comments from my first code reviewer who went on to say the following: "Peer code reviews are like speed bumps on the highway where the ultimate goal is not to impose a fine but for the prevention of speeding violations in general". Translating this to way we code is the ultimate benefit for the whole team. The significant gains are that the person whose code is being reviewed puts in that extra effort to check the missed signals in the sensitivity list and add default states in FSMs when they know their code is going to be put under the spotlight in front of their peers. Many potential bugs get fixed even before the code gets to the review committee. Furthermore, this is the right forum to ensure that people are following the coding guidelines that should be in place. Not only does the code owner gets feedback, the peers in the room generally apply the same lessons to their own code, resulting in an overall improvement and value add.

All said well, the main problem is always the time where code reviews consume significant resources and valuable productive time. In any organization, peer code reviews have to be part of the methodology, be it design or verification.

Self code review is probably more important!

A problem with any code review is the lack of specific targets and the right audience. As said above, in a peer code review people learn from each other however, it is generally not 100% clear what specific targets are to be achieved. Coding guidelines are the easy ones among the possible targets, but they should not be the only targets. Based on my experience, code reviews ideally should come with spec and verification plan reviews. The reviewed spec should be complete and clear enough to define how to assure its correct implementation. The code review plan should be a part of verification plan so that it is a part of the integrated solution to assure the implementation's correctness. Theoretically, the verification plan should include a complete set of conceptual properties to verify. This set should be complete enough to 100% assure the implementation's correctness. Some of the properties should be proven in code review and the rest should be proven with other methods. As an industry, we do not know how to create a theorectically complete spec, and we do not know how to create a theorectically complete verification plan. However, we should at least start taking some steps in the right direction.