Showing posts with label Optimization. Show all posts
Showing posts with label Optimization. Show all posts

System Architect for micro-architecture performance analysis and optimization during functional simulation


System Architect is comprised of a set of powerful, on-demand SystemC-compliant functions and analysis tools that enable micro-architecture performance analysis and optimization during functional simulation. The analysis provides a wide range of valuable information showing how to improve performance and power utilization. Seamlessly linked with Summit's Vista IDE , System Architect enables effective and rapid analysis of system performance and architectural tradeoffs using C and SystemC.

The System Architect API function set can be instrumented into any functional code to track tokens of data, log states and attributes. Textual reports and visualization tools allow designers to analyze actual key performance metrics, such as bus contention, memory utilization, and SW instruction distribution - all during standard functional simulation. These metrics are critical for analyzing micro-architecture bottlenecks, bandwidth limitations, and power tradeoffs.
Key Features:

   * On-demand SystemC-compliant API functions
   * Advanced textual and graphical reports
   * Analysis of data throughput and communication latencies
   * Dynamic resource utilization analysis (such as memories and FIFO's)
   * Software task distribution and processor utilization reports
   * Hardware/Software tradeoff analysis

Interview Question


Some software programming languages allow compilers to perform "short cut" or "short circuit" optimizations on AND and OR operations. In a short-cut AND or OR, the second argument is not evaluated if the first argument evaluates to a controlling value. For example, in evaluating f(x) AND g(y), if f(x) is false, then g(y) will not be evaluted.
  1. Answer whether this optimization is feasible and beneficial in hardware.