Showing posts with label XVGA. Show all posts
Showing posts with label XVGA. Show all posts

Simple XVGA (1024x768) Controller in Verilog


module xvga(clk,hcount,vcount,hsync,vsync);
input clk; // 64.8 Mhz
output [10:0] hcount;
output [9:0] vcount;
output hsync, vsync;
output [2:0] rgb;

reg hsync,vsync,hblank,vblank,blank;
reg [10:0] hcount; // pixel number on current line
reg [9:0] vcount; // line number

wire hsyncon,hsyncoff,hreset,hblankon; // next slide for generation
wire vsyncon,vsyncoff,vreset,vblankon; // of timing signals
wire next_hb = hreset ? 0 : hblankon ? 1 : hblank; // sync & blank
wire next_vb = vreset ? 0 : vblankon ? 1 : vblank;

always @(posedge clk) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hb;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vb;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low
end

// assume 65 Mhz pixel clock
// horizontal: 1344 pixels total
// display 1024 pixels per line
assign hblankon = (hcount == 1023); // turn on blanking
assign hsyncon = (hcount == 1047); // turn on sync pulse
assign hsyncoff = (hcount == 1183); // turn off sync pulse
assign hreset = (hcount == 1343); // end of line (reset counter)
// vertical: 806 lines total
// display 768 lines
assign vblankon = hreset & (vcount == 767); // turn on blanking
assign vsyncon = hreset & (vcount == 776); // turn on sync pulse
assign vsyncoff = hreset & (vcount == 782); // turn off sync pulse
assign vreset = hreset & (vcount == 805); // end of frame

// for frame
always @(posedge clk) begin
if (vblank | (hblank & ~hreset)) rgb <= 0;
else
rgb <= (hcount==0 | hcount==639 | vcount==0 | vcount==479) ? 7 : 0;
end

//for colors (see below)
always @(posedge clk) begin
if (vblank | (hblank & ~hreset)) rgb <= 0;
else
rgb <= hcount[8:6];
end

Color chart:

RGB Color

000 black
001 blue
010 green
011 cyan
100 red
101 magenta
110 yellow
111 white


Example Pixel:


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