Intel buys Infineon wireless
As per the management email sent to Infineon employees this morning, Infineon and Intel have signed the contracts relat…
As per the management email sent to Infineon employees this morning, Infineon and Intel have signed the contracts relat…
Linley Gwennap says "Making it clear that money is no object in its quest to become a major player in the smartph…
Our company today hosted a renowned motivational speaker Mr. John Foley of Blue Angels fame. The title of the talk be…
Infineon Technologies India Pvt Ltd has some openings for full time and contract positions. If you are interested in ap…
ip.access, the leading developer of femtocell and picocell solutions, and AlertMe.com, the pioneer in home energy mana…
The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL…
This new model available in black or white from June 24 has an unchanged pricing at $199 for the 16GB model and $299 fo…
The conference schedule and the registration links can be found here . With a program that is focused on helping you de…
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…
The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to …
Clock skew variation estimation is an important topic in the design and analysis of high-performance digital circuits. …
How can you quantify the impact of dummy fill on post-layout timing? Dummy fill can be inserted into a layout using SO…
Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever…
Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, ma…
How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final d…
How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?
Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage ac…
Constructing a zero-skew clock tree can be formulated as constructing a path-length balanced tree (assuming path delay …
Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a stat…