Yield
A die that passes sort is not a good die. It is a die that is probably good, and the size of that "probably" depends on its yield and on how much of it the test could see. In the illustrative six-die package modelled below, a small die worth 0.6% of the bill of materials accounts for 3.0 of the 7.9 percentage points of package yield loss, because each of its escapes scraps everything bonded around it. That is the economic case for lo…
by
Murugavel Ganesan
November 15, 2026
Verification
The 2024 Wilson Research Group study put first-silicon success at 14% of projects, the lowest level in two decades, so the appeal of agents in verification is easy to see. The published evidence is more mixed than the demos. In one preprint, the same agent flow and model lifted formal coverage by about 22 points on one design and about 8 on another. In another, assertions that compile and prove caught few injected bugs in a typical run. So the…
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Murugavel Ganesan
November 15, 2026
SoC Design
Caliptra is an open root of trust block for data centre SoCs, published as a specification, RTL, ROM and firmware. It began at the Open Compute Project, and its code now lives in the CHIPS Alliance. Adopting it means accepting a contract: the block does a small job carefully, and the SoC team owns almost everything around it. This post walks through that contract for integrators: what the block does, how it boots, which interfaces it exposes, …
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Murugavel Ganesan
November 14, 2026
Wafer Cost
A high-NA EUV scanner costs far more to run per wafer than a low-NA one, yet it can still win on the layers where it replaces several exposures. In the illustrative model below, one high-NA pass costs about 2.3 times one low-NA pass at the scanner, but the finished layer comes out at about €176 per wafer against about €222 for two low-NA passes. That margin is much less secure than it looks. It falls to about €10 once a large die needs stitchi…
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Murugavel Ganesan
November 14, 2026
Liquid Cooling
In April 2026 Google announced its eighth-generation TPU as two chips instead of one. TPU 8t, for large-scale training, has 216 GB of HBM and 128 MB of on-chip SRAM. TPU 8i, for serving and post-training, has 288 GB of HBM and 384 MB of SRAM, with a lower peak compute rating of 10.1 PFLOPs against 12.6. These are Google's figures, and they show the shift plainly: the two jobs no longer want the same balance of memory and compute. This post…
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Murugavel Ganesan
November 13, 2026
Semiconductor Industry
It is tempting to read AI chip trends for 2027 through peak compute alone. For the engineers who design, verify, package and test these parts, the harder limits now sit elsewhere: memory that is short and expensive, packages that are larger than a reticle many times over, links between chips that copper can barely carry, and racks heading towards a megawatt each. This post sets out ten semiconductor trends for 2027, ordered by how directly the…
by
Murugavel Ganesan
November 13, 2026
