SoC Architecture
Hardware coherency is usually presented as a yes or no question about the whole fabric. In practice each master on a SoC gets its own answer, because a CPU cluster, a DMA engine and a neural accelerator share data in very different ways. This post is a decision guide for architects. It puts rough numbers on what hardware coherency costs in storage, traffic and latency, sets out when IO or software coherency is enough, and shows how AMBA CHI, A…
by
Murugavel Ganesan
November 10, 2026
Yield
Silicon lifecycle management, or SLM, is often sold as a simple package: sensors on the chip, a dashboard in the cloud, and a promise that failures will be seen before they happen. Some of that is established engineering, and IBM was steering voltage from on-chip timing monitors in a POWER7 prototype server by 2011. Some of it is still a hope. This post treats SLM as a method. It walks through what a working programme contains from design to f…
by
Murugavel Ganesan
November 10, 2026
Verification
Clock domain crossing checks sit on almost every sign-off list. Reset domain crossing checks often do not, even though an RDC needs no second clock at all. Two flops on one clock, each with its own asynchronous reset, joined by a wire, are enough. Assert the launching flop's reset and its output changes at a moment that has nothing to do with the clock. This post is for RTL and verification engineers. It shows how these bugs arise, why the…
by
Murugavel Ganesan
November 10, 2026
Semiconductor Economics
Google, Amazon, Meta and Microsoft all run their own AI accelerators now, and each publishes figures showing that its chip beats a GPU on cost or efficiency for its own work. It is easy to read that as proof that any large buyer should do the same. Those figures say nothing about what the programme cost or how many chips it took to pay that back. So this post builds the missing sum. It sets a merchant GPU against a custom part using fixed cost…
by
Murugavel Ganesan
November 09, 2026
SoC Design
Post-quantum cryptography usually reaches a chip team as a line in a requirements document: add ML-KEM and ML-DSA. The algorithms have been fixed since NIST published FIPS 203 and FIPS 204 in August 2024, so the open questions are now engineering ones. How many gates, how much SRAM, how many cycles, and what happens to a boot ROM that has to outlive the current signing scheme? Published numbers now answer much of this, although they use differ…
by
Murugavel Ganesan
November 09, 2026
Semiconductor Business
Special report. On 8 November 2026, Nvidia's board said it was opening an independent investigation after news reports that Jensen Huang, the company's founder and chief executive, had been the target of a foreign intelligence effort. On the same day, Huang told employees in an email that he had been unfaithful to his wife. According to the New York Times, citing US officials, the woman at the centre of the reports is a Megaspeed execut…
by
Murugavel Ganesan
November 09, 2026
