Semiconductor Manufacturing
A processor can pass wafer sort, final test, system-level test and burn-in, go into a server, and then return a wrong answer from an ordinary instruction. No machine check fires and no log line appears. The program carries on with a bad number. Meta described one such case in which a CPU core calculated a file size as zero, and files went missing from a database as a result. Google, Meta and Alibaba have now published enough data to show that …
by
Murugavel Ganesan
November 05, 2026
Process Technology
Hybrid bonding joins two pieces of silicon with no solder at all. Flat dielectric meets flat dielectric, copper pads meet copper pads, and an anneal makes the joint permanent. That removes the bump, and with it the floor on how close connections can sit. Research wafers are now bonded at a 200 nm pitch, while shipping server processors use about 9 µm. That gap of roughly forty-five times is the subject of this post. Wafer-to-wafer and die-to-w…
by
Murugavel Ganesan
November 05, 2026
Process Technology
For more than fifty years, power and signals have shared the same side of the chip. Backside power delivery ends that. Power comes up through the back of a thinned wafer, and the front metal stack is left mostly to signals. Intel builds this into 18A as PowerVia, and TSMC plans it for A16 as Super Power Rail. The headline benefit is easy to state: less voltage drop and more room for routing. The harder question for a design team is what change…
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Murugavel Ganesan
November 05, 2026
Photonics
For the last two years the hardest thing to get in AI hardware was not the chip itself but the package around it. TSMC's CoWoS capacity has decided how many accelerators can ship. Now TSMC is reported to be weighing another price rise for that packaging, and on 2 November 2026 Marvell agreed to buy Lumentum for about $115 billion to get into optical interconnect. Together they show where the bottleneck is moving: from packaging to the links…
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Murugavel Ganesan
November 03, 2026
Special Reports
DRAM prices have roughly doubled in 2026, high bandwidth memory (HBM) for 2027 is largely sold out, and phone and PC makers are paying for it. The cause is simple to state: every AI accelerator ships with stacks of HBM, and HBM uses far more wafer capacity per bit than ordinary memory. When the three big memory makers point their fabs at AI, everyone else gets less. This post explains how HBM is built, why it squeezes the rest of the market, w…
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Murugavel Ganesan
November 03, 2026
Video
The Semiconductor Hub is a single website for the people and companies of the semiconductor value chain, from chip design and IP to manufacturing, packaging and test. Our first YouTube video gives a short tour of what it contains: lifecycles, engineering tools, a glossary, news, jobs, a company directory and events, with the page address for each. Watch it below, then visit the Hub; joining is free. Key takeaways The video is the first in …
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Murugavel Ganesan
October 29, 2026
Special Reports
From electronic mirrors to predictive perception: how cameras, silicon, connectivity and AI are reshaping the intelligent vehicle. Automotive cameras have moved from simple reversing aids to the main source of meaning in ADAS perception: lanes, signs, traffic lights and road users. Over five overlapping generations they went from one camera serving one function to many cameras feeding a central AI platform alongside radar and LiDAR. The next …
by
Murugavel Ganesan
October 28, 2026
