Digital systems engineering and perspectives on chip design
Today we are in the age of Digital Convergence seeing a major change in the way digital electronics systems are designe…
Today we are in the age of Digital Convergence seeing a major change in the way digital electronics systems are designe…
Hardware design specialist Libelium opens a new community site for electronics enthusiasts offering a wide range of tut…
In march we had an article covering the Italian project made to fill the gap between Embedded Low Cost and Wireless. T…
The topic of "peer code review" is a widely discussed topic in the context of design verification. I remember…
From the open forum that happened at Infineon today it was made clear that the carved out wireless division will be a s…
The Indian Institute of Science (IISc) and IITs, the premier engineering colleges of India, have earlier joined hands t…
Say YES for changing ONE light to LED at home. Get your organization to say YES to change ONE light per employee to LED…
As per the management email sent to Infineon employees this morning, Infineon and Intel have signed the contracts relat…
Linley Gwennap says "Making it clear that money is no object in its quest to become a major player in the smartph…
Our company today hosted a renowned motivational speaker Mr. John Foley of Blue Angels fame. The title of the talk be…
Infineon Technologies India Pvt Ltd has some openings for full time and contract positions. If you are interested in ap…
ip.access, the leading developer of femtocell and picocell solutions, and AlertMe.com, the pioneer in home energy mana…
The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL…
This new model available in black or white from June 24 has an unchanged pricing at $199 for the 16GB model and $299 fo…
The conference schedule and the registration links can be found here . With a program that is focused on helping you de…
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…
The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to …
Clock skew variation estimation is an important topic in the design and analysis of high-performance digital circuits. …
How can you quantify the impact of dummy fill on post-layout timing? Dummy fill can be inserted into a layout using SO…