- Language for modeling should be VHDL-87
- VHDL-93 keywords should not be used
- Verilog keywords should not be used
- SDF keywords should not be used
- IKOS keywords should not be used
- Allowable replacement characters are forbidden
- Tool specific types may not be used
- Configuration declarations must have the configuration name and the entity name in one line
- Never redefine standard operators, subprograms, attributes, and packages
- Design-internal references must use library work
- Bussed ports of width one are forbidden
- Carefully use real values with PN-generators
- Be aware of operating-system-specific features
- Bussed arithmetic objects use "downto" as their index orientation
- Comparison of arrays must be based on arrays of the same width
- Request external VHDL code suppliers to deliver used arithmetic packages
- Avoid homographs
- Where to use ieee.std_logic_arith and std_developerskit.synth_regpak
- Where to use std_logic_signed and std_logic_unsigned
- Take care of array widths for std_logic_arith operators
- Use conversion functions around arithmetic operators
Note that the restrictions listed below do not apply to pure simulation models and not to testbench models.
- Code for synthesis must match the synthesis subset
- Store package header and body into same file
- Default values for ports, signals, and variables may not be used
- Data types must be synthesizable
- Array ranges must be of type integer
- Integer type objects must be constrained with respect to to their range
- Use standard templates for clocked processes
- Generics must have type integer
- Order of generics in entity, component and instance must be the same
- Place port and generic maps at the component instantiation
- Instantiated component and entity name must be equal, incl. casing
- The sensitivity list for combinational processes must be complete
- Write variables before read in combinational logic
- Bit-wise association of arrays in port maps is not possible in presence of generics
- Embedding scripts as meta comments is not acceptable
- Use only standard meta comments
- Gate instantiation must be encapsulated by separate unit
- Requirements for resource sharing
- Use sensitivity lists instead of wait statements
- Minimize the number of signals of your sensitivity list
- Avoid unnecessary computations within loops
- Remove unnecessary code fragments
- EMC and transmission line effects need not be modeled
- Use abstract, compact coding style in testbench and simulation models
- Minimize the number of processes, signals, and signal assignments
- Replace signals by variables whenever possible
- Inhibit execution of statements where not necessary
- Divide large memories into blocks
- Avoid unnecessary repetition of function calls
- Avoid declaring constants within subprograms
- Always use deallocate(access_obj) to dereference allocated memory
- Do not use guarded signals, guarded assignments, and guarded expressions
- Do not use disconnect, register, and bus
- Do not use configuration specification (“hard binding”)
- Do not use port modes buffer and linkage
- Do not use blocks
- Avoid identifier hiding caused by loop index
- Global signals may be used for testing purposes only
- Recursive use of subprograms is forbidden
- Subprograms may not have any side effects
- Use only well tested functions for object-initialization purposes
- Be aware of the use of the attributes DELAYED, STABLE, QUIET, and TRANSACTION
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