The common reasons quoted by many engineers are simple..
- To check if reset release, initialization sequence and boot-up is proper.
- Since Scan insertions occur during and after synthesis, they are not checked by simulations.
- STA does not analyze asynchronous interfaces.
- Unwarranted usage of wild cards in static timing constraints set false and multi cycle paths where they dont belong. This can also be due to design changes, mis-understanding or typos.
- Usage of create_clock instead of using create_generated_clock between clock domains.
- For switching factor to estimate power.
- X's in RTL sim can be pessimistic or optimistic. Any unintended dependencies on initial conditions can be found through GLS.
- Design changes, wrong understanding of the design can lead to incorrect false paths or multicycle paths in the constraints.
- Can be used to study the activity factor for power estimation.
- It's an excellent feel good quotient that the design has been implemented correctly.
Some design teams use GLS only in a zero-delay, ideal clock mode to check that the design can come out of reset cleanly or that the test structures have been inserted properly. Other teams do fully back annotated simulation as a way to check that the static timing constraints have been set up correctly.
In all cases, getting a gate level simulation up and running is generally accompanied by a series of challenges so frustrating that they precipitate a shower of adjectives as caustic as those typically directed at your most unreliable internet service provider. There are many sources of trouble in gate level simulation. This series will look at examples of problems that can come from your library vendor, problems that come from the design, and problems that can come from synthesis. It will also look at some of the additional challenges that arise when running gate level simulation with back annotated SDF.