Backend physical design Interview Questions

Updated 28 Aug 2023:

I have listed below a set of common interview questions asked mainly in interviews related to physical design or backend activities in ASIC or VLSI chip design process. Typically these interviews start with questions on physical design(PD) flow and goes on to deeper details.

 
* What is signal integrity? How it affects Timing?

Signal integrity (SI) is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage (or current) waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise, distortion, and loss.

Timing refers to the synchronization of signals in a digital system. It is critical to ensure that signals arrive at their destination at the correct time to avoid errors and ensure proper operation of the system.

Signal integrity can affect timing in several ways. For example, if a signal is distorted or delayed due to poor signal integrity, it may arrive at its destination too late or too early, causing timing errors. Crosstalk is another signal integrity issue that can affect timing. Crosstalk occurs when two or more signals interfere with each other, causing distortion and timing errors.

* What is IR drop? How to avoid .how it affects timing?

IR drop is the voltage drop that occurs when current flows through a resistor. In digital circuits, the power supply voltage is distributed through metal wires called the power delivery network (PDN) or power grid. The resistivity of the metal wires used in the PDN increases as their size decreases, leading to an increase in resistance per unit length. As a result, when current flows through the PDN, a part of the applied voltage drops due to resistance, leading to IR drop.

IR drop can cause several issues in digital circuits. For example, when the voltage at a transistor drops due to IR drop, it becomes slower and can impact circuit timing. This can lead to functional failures if it happens on a critical path through a design 13. IR drop can also cause poor performance of the chip due to an increase in delay of standard cells and may cause setup/hold timing violations.

To avoid IR drop issues, you can take several measures such as:

Optimizing the power delivery network: You can optimize the PDN by increasing the width of metal wires and reducing their separation. This will reduce the resistivity of metal wires and minimize IR drop.

Adding decoupling capacitors: Decoupling capacitors can be added to the PDN to reduce IR drop by providing additional charge storage capacity.

Reducing switching activity: Reducing switching activity in digital circuits can help reduce IR drop by minimizing current flow through the PDN.

* What is EM and it effects?

Electromigration (EM) is a phenomenon that occurs in metal wires when a high current density flows through them. It causes the metal atoms to move and accumulate in certain areas, leading to voids or hillocks in the metal wire. This can cause the wire to break or short-circuit, leading to chip failure .

EM is a significant reliability concern in VLSI physical design because it can cause failures in interconnects, which are critical components of digital circuits. Interconnects are used to connect transistors and other components on a chip, and they are typically made of metal wires. As the size of transistors and chips has decreased over time, the current density in interconnects has increased, making EM an increasingly important issue .

To mitigate the effects of EM, several techniques can be used such as:

Wire sizing: Increasing the width of metal wires can reduce the current density and minimize EM 

Wire redundancy: Adding redundant wires can help distribute current and reduce the current density in individual wires .

Power gating: Power gating can be used to turn off unused circuits and reduce current density in interconnects .

* What is floor plan and power plan?

* What are types of routing?

* What is a grid .why we need and different types of grids?

* What is core and how u will decide w/h ratio for core?

* What is effective utilization and chip utilization?

* What is latency? Give the types?

* What is LEF?

* What is DEF?

* What are the steps involved in designing an optimal pad ring?

* What are the steps that you have done in the design flow?

* What are the issues in floor plan?

* How can you estimate area of block?

* How much aspect ratio should be kept (or have you kept) and what is the utilization?

* How to calculate core ring and stripe widths?

* What if hot spot found in some area of block? How you tackle this?

* After adding stripes also if you have hot spot what to do?

* What is threshold voltage? How it affect timing?

* What is content of lib, lef, sdc?

* What is meant by 9 track, 12 track standard cells?

* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?

* What is setup and hold? Why there are ? What if setup and hold violates?

* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?

* How R and C values are affecting time?

* How ohm (R), fared (C) is related to second (T)?

* What is transition? What if transition time is more?

* What is difference between normal buffer and clock buffer?

* What is antenna effect? How it is avoided?

* What is ESD?

* What is cross talk? How can you avoid?

* How double spacing will avoid cross talk?

* What is difference between HFN synthesis and CTS?

* What is hold problem? How can you avoid it?

* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?

* What is partial floor plan?

* What parameters (or aspects) differentiate Chip Design & Block level design??

* How do you place macros in a full chip design?

* Differentiate between a Hierarchical Design and flat design?

* Which is more complicated when u have a 48 MHz and 500 MHz clock design?

* Name few tools which you used for physical verification?

* What are the input files will you give for primetime correlation?

* What are the algorithms used while routing? Will it optimize wire length?

* How will you decide the Pin location in block level design?

* If the routing congestion exists between two macros, then what will you do?

* How will you place the macros?

* How will you decide the die size?

* If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?

* If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?

* In your project what is die size, number of metal layers, technology, foundry, number of clocks?
* How many macros in your design?

* What is each macro size and no. of standard cell count?

* How did u handle the Clock in your design?

* What are the Input needs for your design?

* What is SDC constraint file contains?

* How did you do power planning?

* How to find total chip power?

* How to calculate core ring width, macro ring width and strap or trunk width?

* How to find number of power pad and IO power pads?

* What are the problems faced related to timing?

* How did u resolve the setup and hold problem?

* If in your design 10000 and more numbers of problems come, then what you will do?

* In which layer do you prefer for clock routing and why?

* If in your design has reset pin, then it’ll affect input pin or output pin or both?

* During power analysis, if you are facing IR drop problem, then how did u avoid?

* Define antenna problem and how did u resolve these problem?

* How delays vary with different PVT conditions? Show the graph.

* Explain the flow of physical design and inputs and outputs for each step in flow.

* What is cell delay and net delay?

* What are delay models and what is the difference between them?

* What is wire load model?

* What does SDC constraints has?

* Why higher metal layers are preferred for Vdd and Vss?

* What is logic optimization and give some methods of logic optimization.

* What is the significance of negative slack?

* How the width of metal and number of straps calculated for power and ground?

* What is negative slack ? How it affects timing?

* What is track assignment?

* What is grided and gridless routing?

* What is a macro and standard cell?

* What is congestion?

* Whether congestion is related to placement or routing?

* What are clock trees?

* What are clock tree types?

* Which layer is used for clock routing and why?

* What is cloning and buffering?

* What are placement blockages?

* How slow and fast transition at inputs effect timing for gates?

* What is antenna effect?

* What are DFM issues?

* What is .lib, LEF, DEF, .tf?

* What is the difference between synthesis and simulation?

* What is metal density, metal slotting rule?

* What is OPC, PSM?

* Why clock is not synthesized in DC?

* What are high-Vt and low-Vt cells?

* What corner cells contains?

* What is the difference between core filler cells and metal fillers?

* How to decide number of pads in chip level design?

* What is tie-high and tie-low cells and where it is used?