NOTES:
1. The pipeline has 2 stages where the first stage of the pipeline contains circuit a (executing operation A or B) and the second stage of the pipeline contains circuit b (executing operation C).
2. Stage 2 reads the output of stage 1 as soon as it is available even if the two operations of stage 1 (i.e. A and B) have imbalanced latencies.
3. The pipeline has registers only on the inputs of the stages
4. The performance and cost overhead due to control circuitry (e.g. Mux) is not considered in this preliminary analysis.
Based on your analysis in the earlier post, what is the total time required to execute 100 input parcels sent through the pipeline?
If operation C that has 2 stages are considered to be pipelined, then in total we have 3 stages of pipeline..Tclk=40+5=45 ns...
ReplyDeleteno of jobs to be executd=100
total time=time for 1st job+time for rest 99 jobs..
1st job appears after 3 clock cycles..then after each clock cycle we get output..
so,, total time=(3*45)+(99*45)=4590ns.
am i missing somewhere???
But it is mentioned that no registers in the output side so Tclk = 30+5=35
ReplyDeleteTotal time=time for 1st job+time for rest 99 jobs..
1st bit to reach output 3 clock cycle
Total time =(35*3)+(99*35)= 3372ns