Low Voltage Is Key To Energy-Efficient Chip - Part II

I have managed to gather a real doc on the recently announced low voltage chip...

These are some of the important details...

• This was a PhD Thesis for very low voltage operation
• 8T SRAM to avoid erasing of content which reading
• Supply voltage 0.3-0.6V (derived from 1.2V by DC-DC converter)
• Variation e.g. by random dopant fluctuations that required redesign of library
• SubVt logic cell library was developed and used
• 62 cells with limited fanin of 3
• Small cells may double in size compared to regular library
• e.g. Upsizing of keeper cells in flipflops and resizing of T-gates
• Average area overhead ~1.7x
• SubVt timing is slow!
• Monte Carlo simulation of selected path
• Handcrafted timing signoff methodology

Now here is the Link!