ST Microelectronics - Interview Questions

• What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)?
• What was the average design cycle time for your designs?
• What part are your areas of interest in physical design?
• Explain ECO (Engineering Change Order) methodology used in your projects.
• Explain CTS (Clock Tree Synthesis) flow used in your projects.
• What kind of routing issues did you face in your projects? Mention the recent one?
  
• How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done?
  
• How do you set OCV (On Chip Variation) in the tool you used?
  
• How is timing correlation done before and after place and route?
• If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
• Define hash/ @array in perl.
• Using TCL (Tool Command Language, Tickle) how do you set variables?
• What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
• What are nanoroute options for search and repair?
• What were your design skew/insertion delay targets?
• How is IR drop analysis done? What are various statistics available in reports?
• Explain pin density/ cell density issues, hotspots?
• How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
• What is the command for setting multi cycle path?
• If hold violation exists in design, is it OK to sign off design? If not, why?

Source:
[http://vlsifaq.blogspot.com/]
Raj - Sequence Design

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